應用於物聯網之低複雜度空間調變收發機設計與實現;Design and Implementation of a Low-complexity Spatial Modulation Transceiver for Internet of Things

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Title:	應用於物聯網之低複雜度空間調變收發機設計與實現;Design and Implementation of a Low-complexity Spatial Modulation Transceiver for Internet of Things
Authors:	葉宗諺;Yeh, Tsung-Yen
Contributors:	電機工程學系
Keywords:	物聯網;空間調變;收發機;IoT;Spatial Modulation;Transceiver
Date:	2018-08-10
Issue Date:	2018-08-31 14:54:58 (UTC+8)
Publisher:	國立中央大學
Abstract:	IoT(Internet of Things)的應用日趨變多，如智慧家庭、遠距照護、智慧城市等，而符合其應用的特性是要低功耗，長距離傳輸的特點。低功耗是為了解決充電不易或是增加電池壽命。長距離傳輸是讓感應器(sensor)可以分布更廣，加大應用可能性。此論文的無線通訊收發機，是在IEEE 802.15.4的規範下設計封包形式，使用了空間調變(spatial modulation)，增加了頻譜效率(spectral efficiency)但又不增加射頻前端的複雜度。考慮的效應有多重路徑衰減，載波頻率偏移(CFO)和雜訊(AWGN)。接收機的功能區塊分成三大塊。首先是粗略同步，使用了前置序列的特性來偵測邊界且同時估測了CFO的初始相位，硬體部分將閒置運算的硬體重複使用，使得CORDIC、乘法器和延遲器的個數減少33%。接著是精確補償，進一步修正且同時補償相位，亦為多天線模式做了通道估測且具有持續的殘餘相位的補償功能，在硬體的部分也將閒置的硬體重複利用，使得CORDIC和乘法器的個數減少67%，而查表大小，也利用對稱性和重複性來降低表的大小，讓查表的使用位元數減少75%。最後一塊是資料還原，在多天線模式下使用最大似然偵測(maximum likelihood detection)來偵測OQPSK的空間調變訊號，而其硬體的實現由演算法化簡與分類重複運算，不需用乘法器即可完成運算，在比較器的部分利用延遲(latency)和資料分組，使得比較器使用數量減少73%。以上利用定點數模擬的結果，來完成硬體，根據合成結果，操作時脈最快可達7.594 MHz，使得傳輸速度滿足3Mbps需求。;This thesis presents an O-QPSK transceiver with 2×2 spatial modulation for Internet of Things applications. The communication system uses 2.4GHz carrier frequency with a 3Mbps data rate. The transceiver uses 2×2 MIMO transmission with spatial modulation. The receiver is separated into three main blocks, including coarse synchronization, fine synchronization and data recovery. First, for coarse synchronization, we decrease the usage of hardware such as CORDICs, multipliers, and DFFs about 33% to achieve symbol boundary detection. Then, for the fine synchronization, we have phase compensation, residual phase tracking to compensate received signals and channel estimation for data recovery. We also reuse the hardware, like CORDICs and multipliers, so about 67% hardware is reduced. As for the look up table, we take advantage of the symmetry and repetition so that our table size is reduced by 75%. Last but not least, for the data recovery block, maximum likelihood detection is used for recovering signal. By simplifying our algorithm, we adopt no multiplier in this block. Due to the trade-off between the number of comparators and latency, we can eliminate the comparators by 73%. According to the synthesis result, the maximum clock frequency is 7.594 MHz and the implementation can achieve the data rate of 3Mbps.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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