憶阻式內容循址記憶體之測試;Testing of Memristor-Based Content Addressable Memories

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Title:	憶阻式內容循址記憶體之測試;Testing of Memristor-Based Content Addressable Memories
Authors:	鄧力瑋;Deng, Li-Wei
Contributors:	電機工程學系
Keywords:	憶阻器;內容循址記憶體;Memristor;CAM;TCAM;Fault model
Date:	2018-08-21
Issue Date:	2018-08-31 14:55:54 (UTC+8)
Publisher:	國立中央大學
Abstract:	內容循址記憶體 (Content-Addressable Memory, CAM) 為一種被廣泛運用在網絡系統中的元件。為了解決與功耗和面積的問題，許多非揮發性的內容循址記憶體因此被提出。在這些非揮發性的內容循址記憶體中，憶阻式的內容循址記憶體是一個不錯的候選元件。但是，現存的憶阻式內容循址記憶體其細胞架構和半導體式內容循址記憶體其細胞架構有很大的不同，而且，也因為憶阻器引發了一些錯誤機制。因此，憶阻式內容循址記憶體需要有效的測試方法及其錯誤模型。在此篇論文，我們透過加入各種不同的電子性缺陷，像是電阻性開路、電阻性短路、電晶體開路、電晶體短路、電阻式橋接，來定義 5T-2R 憶阻式內容定址記憶體。然後，我們提出了一種行軍式測試演算法 March-MCAM 來涵蓋我們所定義的 5T2R 憶阻式內容循址記憶體之比對性錯誤模型。 March-MCAM 需要 6N 的寫入指令及 (14N+2B) 的比對指令來涵蓋一個 NxB-bit 5T-2R 憶阻式內容循址記憶體的比對性錯誤模型，在此 14N 代表的是兩個比對指令需要執行 7 次。但是，憶阻式內容循址記憶體有許多不同的細胞架構，若要人工手動去一一測試，會需要相當多的時間。因此，在論文的第二個部分我們提出了一個內容循址記憶體自動化測試的方法。最後，我們提出了內容循址記憶體的行軍式測試產生之演算法自動化的方法。此方法運用了讀與搜尋偵測之等效 Read-Compare Detection Equivalence (RCDE) 來減少產生時間。最後，分析結果顯示，產生所需要的時間比沒用 RCDE 的方法快了 2 倍。;Content addressable memory (CAM) is one widely used component in network systems. Recently, memristor-based CAMs have been proposed to cope with the power and area issues of conventional CMOS-based CAMs. Among them, memristor-based CAM is considered as a good candidate. However, existing memristor-based CAM cell structures are much different from conventional CMOS-based CAM structures. Also, the fabrication process of memristor device may induce new failure mechanisms. Therefore, effective fault modeling and testing techniques for memristor-based CAMs are imperative. In this thesis, we define comparison faults for 5T-2R memristor-based ternary CAMs (mrTCAMs) by injecting the electrical defects of resistive open, short, transistor stuck-on, transistor stuck-open, and bridge. Then, a March-like test, March-MCAM, is proposed to cover the comparison faults of 5T-2R mrTCAMs. The March-MCAM requires 6N Write operations and (14N+2B) Compare operations to cover 100% comparison faults of an N×B- bit 5T-2R mrTCAM array where 14N represents 2 compare operaitons are executed 7 times. However, different cell structures were proposed to realize mrTCAMs. It is time-consuming to manually do the fault modeling and test algorithm design. Therefore, we also propose an automation method for the fault modeling of CAMs. Finally, we propose a test algorithm generation method for CAMs. The proposed method uses the Read-Compare Detection Equivalence (RCDE) concept to reduce the test generation time. Analysis results show that the proposed method can achieve about 2 times of generation time reduction in comparison with the method without using RCDE concept.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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