匯流排上的時間延遲及交談失真的偵錯設計技巧; A Design for Diagnosis technique for the Delay and Crosstalk Measurement of On-chip Bus

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Title:	匯流排上的時間延遲及交談失真的偵錯設計技巧;A Design for Diagnosis technique for the Delay and Crosstalk Measurement of On-chip Bus
Authors:	陳耿男;Gan-Nan Chen
Contributors:	電機工程研究所
Keywords:	交談失真;匯流排;時基異變;可偵錯設計技巧;時間延遲;crosstalk;bus;jitter;design for diagnosis;delay
Date:	2000-06-12
Issue Date:	2009-09-22 11:40:36 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	篇論文主要是對晶片上匯流排提出的可偵錯技術（Design for Diagnosis－DFD）。這個技術重要的特點之一就是使用數位的方法來對晶片上匯流排作時間延遲及交談失真的測試和偵錯。數位時間延遲量測模組（Digital Delay Measurement Module－DMM）可用來處理時間延遲的量測。它計數相位偵測器輸出的工作週期（Duty Cycle）來決定時間的延遲。這工作周期是測試信號和延遲信號互斥。至於偵錯組態可用來決定是匯流排上的驅動器、接收器、或是連接線線發生錯誤。交談失真雜訊的量測可用來對此種現象作進一步的分析。最後，設計一顆全客戶製作（Full custom design）的晶片來對上述的各種功能作驗証及模擬。 This paper is about a design for diagnosis (DFD) technique for the on-chip bus wires. It uses digital method to measure the delay and crosstalk for the testing and diagnosis of on-chip bus wires. For the delay measurement, the digital delay measurement module (DMM) counts the duty cy-cle of the phase detector (PD) output, which is the exclusive-or of the test signal and the delayed sig-nal, to determine the delay. The diagnosis con-figuration can use to identity whether the drivers, receivers, or wires are in fault. The crosstalk noise measurement can be used to analysis the phenomenon. Finally, a full custom chip design is implemented to verify and simulate the above functions
Appears in Collections:	[電機工程研究所] 博碩士論文

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