應用於FR3頻段互補式金氧半導體堆疊式功率放大器暨使用開關鍵控調變器之發射機與連續F類氮化鎵功率放大器研製;Design and Implementation of CMOS Stacked Power Amplifier, On-Off Keying Modulation Transmitter, and Continuous Class-F GaN Power Amplifier for FR3 Band Applications

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題名:	應用於FR3頻段互補式金氧半導體堆疊式功率放大器暨使用開關鍵控調變器之發射機與連續F類氮化鎵功率放大器研製;Design and Implementation of CMOS Stacked Power Amplifier, On-Off Keying Modulation Transmitter, and Continuous Class-F GaN Power Amplifier for FR3 Band Applications
作者:	蔡舜羽;Tsai, Shun-Yu
貢獻者:	電機工程學系
關鍵詞:	功率放大器;發射機;射頻IC;Power Amplifier;Transmitter;RFIC
日期:	2024-10-22
上傳時間:	2025-04-09 17:48:11 (UTC+8)
出版者:	國立中央大學
摘要:	本論文使用台灣積體電路製造股份有限公司 (tsmcTM) 0.18-µm CMOS製程設計的互補式金氧半導體堆疊式功率放大器與90-nm CMOS製程的使用開關鍵控調變器之發射機，以及穩懋半導體公司(WINTM)之0.25-µm GaN製程設計的連續F類氮化鎵功率放大器。第一顆晶片提出應用於X頻段之互補式金氧半導體功率放大器，透過堆疊式結構增加輸出擺幅，並適當選擇偏壓點提升線性度，拉近了飽和輸出功率與1-dB增益壓縮點功率的距離。其操作頻寬為8.5 - 10.5 GHz，最大傳輸增益為15.1 dB，最大輸出功率為24.4 dBm，1-dB增益壓縮點輸出功率為21.8 dBm，最高附加效率為16.2%，晶片面積為2.6 mm2 (2.23 mm × 1.18 mm) 。第二顆晶片提出使用開關鍵控之發射機電路，本地震盪源使用一變壓器回授壓控震盪器，達到穩定輸出訊號，並控制調變器的開關，獲得穩定的高速調變訊號，最後透過放大器將訊號送出，操作頻率為9.1 – 10.01 GHz，最快資料傳輸速率為7.2 Gbps，能量轉換效率為4 pJ/bit，在位移頻率為1MHz下，最佳相位雜訊為-114.8 dBc/Hz，輸出功率為3.4 dBm，隔離度為34.4 dB，晶片面積為0.81 mm2 (1.24 mm × 0.66 mm)。第三顆晶片為連續F類功率放大器，輸出匹配網路採用F類連續模式，藉以提升電路整體效率。其操作頻寬為10 -12 GHz，最大傳輸增益為10 dB，最大輸出功率為35.4 dBm，最高附加效率為28.7%，晶片面積為2.5 mm2 (2.5 mm × 1 mm) 。 ;This thesis presents the design of a complementary metal-oxide-semiconductor (CMOS) stacked power amplifier utilizing TSMC′s 0.18-µm CMOS process, an on-off keying (OOK) modulation transmitter employing a 90-nm CMOS process, and a continuous Class-F GaN power amplifier implemented with WIN′s 0.25-µm GaN process The first chip is a CMOS power amplifier designed for X-band applications. Utilizing a stacked structure increases the output swing and enhances linearity by selecting optimal bias points, thereby reducing the gap between the saturated output power and the 1-dB gain compression point. It operates within a bandwidth of 8.5 - 10.5 GHz, achieving a maximum gain of 15.1 dB, a maximum output power of 24.4 dBm, an output power of 21.8 dBm at the 1-dB compression point, and a peak power-added efficiency (PAE) of 16.2%. The chip occupies an area of 2.6 mm² (2.23 mm × 1.18 mm). The second chip is a transmitter circuit utilizing on-off keying (OOK) modulation. A transformer-feedback voltage-controlled oscillator (VCO) serves as the local oscillator, generating a stable output signal. Externally controlled modulator switches produce a high-speed modulated signal, which is then amplified and transmitted via a power amplifier. The circuit operates at a frequency range of 9.1 - 10.01 GHz, supports a maximum data rate of 7.2 Gbps, and achieves an energy efficiency of 4 pJ/bit. The phase noise is -114.8 dBc/Hz at a 1 MHz offset, with an output power of 3.4 dBm and isolation of 34.4 dB. The chip area is 0.81 mm² (1.24 mm × 0.66 mm). The third chip is a continuous Class-F power amplifier, incorporating a continuous-mode F matching network to enhance overall circuit efficiency. It operates within a bandwidth of 10 - 12 GHz, achieving a maximum gain of 10 dB, a maximum output power of 35.4 dBm, and a peak power-added efficiency (PAE) of 28.7%. The chip occupies an area of 2.5 mm² (2.5 mm × 1 mm).
顯示於類別:	[電機工程研究所] 博碩士論文

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