應用於C/X頻帶之低功耗寬頻接收機前端電路之研製;Design and Implementation of a Low-Power, Wideband Receiver Front End for C/X Band Applications

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Title:	應用於C/X頻帶之低功耗寬頻接收機前端電路之研製;Design and Implementation of a Low-Power, Wideband Receiver Front End for C/X Band Applications
Authors:	賴薈之;LAI, HUI-CHIH
Contributors:	電機工程學系
Keywords:	低雜訊放大器;LNA
Date:	2024-11-18
Issue Date:	2025-04-09 17:48:25 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文使用台灣積體電路製造股份有限公司 (tsmcTM) 018-µm CMOS 製程設計，論文總共3顆晶片，包含兩顆應用於C/X 頻帶之寬頻低雜訊放大器與一顆應用於C/X頻帶寬頻之接收機研製。第一顆電路輸入匹配使用閘極與源極退化電感組成的變壓器來提升高頻的增益並改善輸入寬頻響應，第二級則使用疊接結構來實現高增益，用電感峰值技術，使增益平坦性提升，在輸出匹配減少功耗的同時提升輸出的匹配及改善增益平坦度，並縮小晶片面積，實現應用於C/X頻段的寬頻低雜訊放大器。此電路量測最高增益為13.45 dB，3-dB頻寬從5.7 - 13.1 GHz，最低雜訊指數為3.06 dB，線性度P1dB量測結果為-14 ~ -16.5 dBm，線性度IIP3則為-4 ~ -7 dBm，量測功耗為13.63 mW，晶片面積為1.17 × 1 mm^2。第二顆電路則是電阻回授式反向器之寬頻低雜訊放大器，第一級為電阻回授式反向器搭配閘極與源極組成的變壓器來達到寬頻的輸入匹配，在第二級為了提高增益使用疊接架構，再加上汲極與源極組成的變壓器，來改善增益平坦度。雜訊匹配的部分針對高頻進行優化，通過犧牲低頻的雜訊來優化高頻的雜訊匹配，實現整個頻帶內更平坦的雜訊匹配。此電路量測到最高增益為12.01 dB，3-dB頻寬從4.5 - 12.6 GHz，最低雜訊指數為3.59 dB，線性度P1dB量測結果為-10 ~ -15 dBm，線性度IIP3則為-1 ~ -5 dBm，量測功耗為12.69 mW，晶片面積為0.92 × 0.84 mm^2。第三顆電路為應用於C/X頻帶寬頻之接收機，整體接收機前端包含四個子電路：第一級為寬頻低雜訊放大器，使用第二顆的寬頻低雜訊放大器，第二級為雙共振點的寬頻巴倫，第三級為雙平衡被動混頻器，第四級則為兩級的轉阻放大器(TIA)。該架構有效提升信號隔離度與增益平坦度，並減少功耗。此電路量測最高轉換增益(Conversion Gain)為29.96 dB，3-dB頻寬從4 – 11.5 GHz，雙邊帶雜訊指數為7.3 dB，線性度P1dB量測結果為-24 ~ -26 dBm，線性度IIP3則為-11 ~ -23 dBm，量測功耗為25.35 mW，晶片面積為1.92 × 0.84 mm^2。 ;This thesis presents the design and development of three integrated circuits using the 0.18-µm CMOS process provided by Taiwan Semiconductor Manufacturing Company (tsmc™). The circuits include two wideband low-noise amplifiers (LNAs) targeting the C/X bands and a wideband receiver operating in the same frequency range. The first chip is a wideband LNA designed using a transformer comprising gate and source degeneration inductors for input matching. This approach enhances high-frequency gain and broadens the bandwidth. A cascode structure is employed in the second stage to achieve high gain, with inductive peaking techniques used to improve gain flatness. This design optimizes power consumption, output matching, and chip area, while also flattening the gain. Measured results show a maximum gain (S21) of 13.45 dB, a 3-dB bandwidth spanning from 5.7 to 13.1 GHz, a minimum noise figure (NF) of 3.06 dB, a P1dB between -14 and -16.5 dBm, and an IIP3 ranging from -4 to -7 dBm, with a power consumption of 13.63 mW. The chip area is 1.17 × 1 mm². The second chip is a wideband LNA featuring a resistive feedback inverter. The first stage combines the feedback inverter with a gate-source transformer to achieve wideband input matching, while the second stage employs a cascode structure and a drain-source transformer to enhance gain flatness. The design optimizes noise matching at high frequencies, sacrificing some low-frequency performance to achieve uniform noise matching across the bandwidth. Measured results show a maximum gain (S21) of 12.01 dB, a 3-dB bandwidth from 4.5 to 12.6 GHz, a minimum noise figure (NF) of 3.59 dB, a P1dB between -10 and -15 dBm, and an IIP3 from -1 to -5 dBm, with a power consumption of 12.69 mW. The chip area is 0.92 × 0.84 mm². The third chip is a wideband receiver designed for the C/X band. The receiver’s front end comprises four sub-circuits: a wideband LNA (utilizing the second circuit′s design), a wideband balun with dual resonance points, a double-balanced passive mixer, and a two-stage transimpedance amplifier (TIA). This architecture enhances signal isolation, gain flatness, and reduces power consumption. Measured results show a maximum conversion gain of 29.96 dB, a 3-dB bandwidth of 4 to 11.5 GHz, a minimum double-sideband noise figure (NFdSB) of 7.3 dB, a P1dB between -24 and -26 dBm, and an IIP3 ranging from -11 to -23 dBm, with a power consumption of 25.35 mW. The chip area is 1.92 × 0.84 mm².
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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