合成孔徑雷達背向投影演算法效能分析與硬體實作;Performance Analysis and Hardware Implementation of Back Projection Algorithm for Synthetic Aperture Radar

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题名:	合成孔徑雷達背向投影演算法效能分析與硬體實作;Performance Analysis and Hardware Implementation of Back Projection Algorithm for Synthetic Aperture Radar
作者:	張家豪;Chang, Chia-Hao
贡献者:	電機工程學系
关键词:	合成孔徑雷達;背向投影演算法;Synthetic Aperture Radar;Back Projection Algorithm
日期:	2025-01-15
上传时间:	2025-04-09 17:49:41 (UTC+8)
出版者:	國立中央大學
摘要:	合成孔徑雷達通常裝置在飛機或衛星上，隨著載體移動對地表發射訊號，回波訊號經由演算法處理，可以不受天氣狀況影響，產生高解析度的二維成像。在成像演算法方面，研究兩種雷達掃描模式下適用的演算法，聚光燈掃描模式下包含了極座標演算法與背向投影演算法；帶狀掃描模式下為背向投影演算法與測距都普勒演算法。首先，以點目標物的成像模擬與成像標準進行比較，確認效能。接著，對於帶狀掃描模式下真實衛載雷達資料，由於背向投影演算法需要額外的雷達位置與數位高度模型才能進行成像，設計了一個線性地理關係模型以解決此問題，並比較背向投影演算法與測距都普勒演算法的成像效能。基於上述模擬，最終選定通用掃描模式且成像效能更好的背向投影演算法，同時為了達成即時成像的目標，需要設計硬體加速器以縮短處理時間，硬體上主要包含兩個區塊，測距方向壓縮與方位方向處理。在測距方向壓縮，改為使用頻域匹配濾波器提升計算效率，而為了增加可配置性，採用座標旋轉數位計算方法來取代乘法器與查找表，實現複數乘法。在方位方向處理，是將訊號格點處理為成像格點，步驟包含訊號內插、都普勒效應補償與累加，為了避免頻繁從高頻寬記憶體存取資料，以降低能量消耗與提升資料使用效率，將1024×1024的成像切分為多個固定大小的子區域，基於資料排程分析，決定長形子區域尺寸，並採用對角左下的處理順序，可以有效避免從記憶體重複讀取相同資料，與直接採用方形處理子區域以及測距方向水平處理流程相比有效降低外部記憶體存取次數至8/896。;Synthetic Aperture Radar (SAR) is a payload on aircrafts or satellites for surveillance. It transmits signals to the earth′s surface as the platform moves. The echo signals are processed through imaging algorithms to generate high-resolution 2D image that is unaffected by weather. Two types of radar scan modes are studied. In spotlight scan mode, we investigate Polar Format Algorithm (PFA) and Back Projection Algorithm (BPA). In stripmap scan mode, the BPA and the Range Doppler Algorithm (RDA) are employed and compared. First, the imaging performance is evaluated through simulation of reflection from a point target. Next, the real satellite SAR data in the stripmap scan mode are used. Although the BPA requires additional radar position and digital elevation model for imaging, a linear geographic relationship model is developed to address this issue. The imaging performance of the BPA is compared to that of RDA. Based on the simulations, BPA is ultimately selected for its compatibility with both scan modes and superior imaging performance. To achieve real-time imaging, a hardware accelerator is designed to reduce processing time. The hardware consists of range compression and azimuth processing blocks. In range compression, a frequency domain matched filter is used to improve efficiency. To enhance configurability, the COordinate Rotation DIgital Computer (CORDIC) is adopted to replace multipliers and look-up tables. In azimuth processing, signal grids are transformed into image grids through signal interpolation, Doppler compensation, and accumulation. To reduce frequent data access from external high bandwidth memory and the energy consumption, the imaging size 1024×1024 is divided into multiple fixed-size tiles. Based on data scheduling procedure analysis, a rectangular tile size with diagonal lower left processing sequence can effectively eliminate data reloading redundancy and achieve a reduced data access ratio of only 8/896.
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