| 摘要: | 在傳統增強型p型氮化鎵閘極結構中，p型氮化鎵閘極為蕭特基接觸，臨界電壓值大約限制在1 V ~ 2 V，且汲極輸出電流密度也較低。本篇論文主要是研究加入一層氮化矽作為閘極絕緣層的新型增強型之金屬-絕緣層-半導體與p型氮化鎵結合的閘極元件，在新型結構中，兩個p型氮化鎵中間形成空乏型之金屬-絕緣層-半導體閘極的結構，目的是增加下方通道處的載子濃度，兩側為增強型之金屬-絕緣層- p型氮化鎵閘極結構，目的是調變導帶，使其為常關型元件。製程元件後透過量測元件靜態與動態特性完成特性分析，並利用Silvaco TCAD模擬研究新閘極結構的物理性分析。
在不同閘極金屬長度之新型增強型之金屬-絕緣層-半導體與p型氮化鎵結合的閘極元件中，可以觀察到隨著閘極金屬長度的增加，可以有較好控制下方通道的能力，使最大汲極輸出電流增加、導通電阻下降、電流開關比提升、轉導增益值增加。
相較於傳統增強型之金屬-絕緣層- p型氮化鎵閘極元件，新型增強型之金屬-絕緣層-半導體與p型氮化鎵結合的閘極元件改善汲極電流密度和轉導增益值達299 % (114.6 mA/mm)和214 % (56.4 mS/mm)，導通電阻也降至17.9 Ω·mm。此外，元件的電流開關比也從1.0 × 104提升至6.0 × 108，說明新型增閘極元件可以提高閘極下方通道的控制能力，進而改善元件的導通特性。在元件動態特性量測中，閘極延遲、閘極和汲極延遲量測可以觀察到，傳統增強型之金屬-絕緣層- p型氮化鎵閘極元件的電流崩塌效應以及導通電阻退化較為嚴重，而新型閘極元件可以確實改善電流崩塌效應。
最後，關於絕緣層/半導體介面品質之分析，使用電容-電壓遲滯量測之曲線偏移量與電導法兩種方法來進行介面缺陷密度的萃取。結果呈現金屬-絕緣層-半導體二極體在SiN/AlGaN的介面缺陷密度是顯著增加高於AlGaN/GaN的介面缺陷密度，說明因蝕刻電漿所造成的表面傷害是非常巨大。此外，複雜的新型金屬-絕緣層-半導體與p型氮化鎵結合的閘極結構對於SiN/AlGaN和SiN/p-GaN綜合的介面缺陷密度，仍需再進行優化的研究。
;In the conventional E-mode p-GaN gate structure, the p-GaN gate has Schottky contact, the threshold voltage value is limited to about 1 V ~ 2 V, and the drain output current density is also low. This paper mainly studies a novel E-mode MIS p-GaN gate HEMT that adds a layer of silicon nitride as the gate insulator layer. In the novel structure, a depletion mode metal-insulator-semiconductor gate structure is formed between two p-GaN in order to increase the carrier concentration in the 2DEG channel. On both p-GaN sides are enhanced metal-insulator-p-GaN gate structures to modulate the conduction band to make it a normally-off device. After the devices are fabricated, characteristic analysis is completed by measuring the static and dynamic characteristics of the device, and the physical analysis of the novel gate structure is studied using Silvaco TCAD simulation.
In the novel E-mode gate device combining metal-insulator-semiconductor and p-GaN with different gate metal lengths, it can be observed that as the gate metal length increases, the 2DEG channel can be better controlled. Ability to increase the ID,max, reduce the RON, increase the Ion/Ioff, and increase the Gm.
Compared with the conventional E-mode MIS p-GaN gate HEMT, the novel E-mode MIS p-GaN gate HEMT improves the drain current density and Gm reach 299 % (114.6 mA/mm) and 214 % (56.4 mS/mm), and the RON is also reduced to 17.9 Ω·mm. In addition, Ion/Ioff of the device also increased from 1.0 × 104 to 6.0 × 108, indicating that the novel gate device can improve the control capability of the channel below the gate, thereby improving the conduction characteristics of the device. Measurement of device dynamic characteristics, gate delay, gate and drain delay measurements can observe the current collapse effect and RON degradation of conventional E-mode MIS p-GaN gate HEMT is more serious, and novel gate device can indeed improve the current collapse effect.
Finally, regarding the analysis of the insulator layer/semiconductor interface quality, the curve offset of capacitance-voltage hysteresis measurement and the conductance method, were used to extract the interface state density. The results show that the interface state density of the metal-insulator-semiconductor diode in SiN/AlGaN is significantly higher than that of AlGaN/GaN, indicating that the surface damage caused by etching plasma is huge. In addition, the complex novel metal-insulator-semiconductor and p-GaN gate structure still needs to be optimized for the comprehensive interface state density of SiN/AlGaN and SiN/p-GaN. |
