| 摘要: | 本研究採用穩懋0.25 μm氮化鎵與0.15 μm砷化鎵高電子遷移率電晶體(HEMT)商用製程，分別設計適用於Sub-6 GHz頻段以及毫米波頻段的class-AB−單晶片微波積體電路(MMIC)功率放大器。
第一片晶片使用0.25 μm GaN HEMT技術製作，為一單級class-AB功率放大器，其電路結構由單一電晶體搭配電感、電阻和電容等集總元件組成輸入、輸出匹配電路。該放大器操作頻率為3.5 GHz，模擬設計可達37.41 dBm的輸出功率，功率附加效益 (PAE) 為53.07 %；晶片直接量測結果顯示最大輸出功率為29.39 dBm，對應的功率附加效益為16.56 %。在5G NR QPSK和16-QAM調變訊號量測中ACPR分別為 −38 與 −39 dBc，另外均方根向量誤差失真 (EVM) 則是2.19%與2.04%。
第二片晶片使用0.15 μm GaAs pHEMT技術製作，為一兩級class-AB功率放大器，並結合傳輸線、電阻和電容組成輸入、輸出與級間匹配電路；該放大器設計操作頻率在30 GHz，模擬設計可達到23.19 dBm的飽和輸出功率 (Psat) ，最大功率附加效益32.69%，以及1-dB壓縮點輸出功率 (OP1dB) 21.34 dBm。晶片直接實測結果顯示在28 GHz操作頻率下飽和輸出功率為21.46 dBm，最大功率附加效益可達33.54%，1-dB壓縮點輸出功率為14.70 dBm；在30 GHz操作頻率下飽和輸出功率僅有15.91 dBm，最大功率附加效益為6.53%，1-dB壓縮點輸出功率則為13.40 dBm。在5G NR QPSK、16-QAM與256-QAM調變訊號量測中ACPR分別為−22 dBc、−23 dBc與−33 dBc，依照5G NR Release 15標準，三種調變訊號EVM最大容許值：QPSK為17.5%、16-QAM為12.5%、256-QAM則為3.5%，各值所對應到的輸出功率各為14.27 dBm、13.18 dBm與3.71 dBm。
;This study employs the WIN Semiconductors′ 0.25 μm GaN and 0.15 μm GaAs high electron mobility transistor (HEMT) commercial processes to design linear Class AB monolithic microwave integrated circuit (MMIC) power amplifiers for the Sub-6 GHz band and the millimeter-wave band, respectively.
The first chip is fabricated using the 0.25 μm GaN HEMT technology and is designed as a single-stage Class AB power amplifier. Its circuit structure comprises a single transistor paired with lumped components such as inductors, resistors, and capacitors to form input and output matching networks. The amplifier operates at a frequency of 3.5 GHz, with theoretical expectations of achieving an output power of 37.41 dBm and a power-added efficiency (PAE) of 53.07%. However, actual measurements show a maximum output power of 29.39 dBm with a corresponding PAE of 16.56%. During 5G NR QPSK and 16-QAM modulated signal testing, the adjacent channel power ratio (ACPR) is approximately -38 and -39 dBc, and the root mean square error vector magnitude (EVM) distortion values are 2.19% and 2.04%, respectively.
The second chip is fabricated using 0.15 μm GaAs pHEMT technology and is designed as a two-stage Class AB power amplifier. Its circuit structure incorporates two transistors, with input, output, and inter-stage matching networks formed using transmission lines, resistors, and capacitors. The amplifier is designed to operate at a frequency of 30 GHz, with theoretical expectations of achieving a saturated output power (Psat) of 23.19 dBm, a maximum power-added efficiency (PAE) of 32.69%, and a 1-dB compression point output power (OP1dB) of 21.34 dBm. However, measurement results show that at an operating frequency of 28 GHz, the saturated output power is 21.46 dBm, with a maximum PAE of 33.54% and an OP1dB of 14.70 dBm. At 30 GHz, the measured saturated output power drops to 15.91 dBm, the maximum PAE is 6.53%, and the OP1dB is 13.40 dBm. In the 5G NR QPSK, 16-QAM, and 256-QAM modulated signal measurements, the ACPR values are −22 dBc, −23 dBc, and −33 dBc, respectively. According to the 5G NR Release 15 standard, the maximum allowable EVM for these three modulation signals is 17.5% for QPSK, 12.5% for 16-QAM, and 3.5% for 256-QAM. The corresponding output power levels are respectively 14.27 dBm, 13.18 dBm, and 3.71 dBm. |
