應用於選擇性諧波消除脈波寬度調變於多電平逆變器的深度神經網路之晶片設計與實現;Chip Design and Implementation of a Deep Neural Network Applied to Selective Harmonic Elimination Pulse Width Modulation for Multilevel Inverter

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題名:	應用於選擇性諧波消除脈波寬度調變於多電平逆變器的深度神經網路之晶片設計與實現;Chip Design and Implementation of a Deep Neural Network Applied to Selective Harmonic Elimination Pulse Width Modulation for Multilevel Inverter
作者:	陳德帆;Chen, De-Fan
貢獻者:	電機工程學系
關鍵詞:	選擇性諧波消除脈波寬度調變;多電平逆變器;深度神經網路
日期:	2025-11-21
上傳時間:	2026-03-06 18:55:42 (UTC+8)
出版者:	國立中央大學
摘要:	在現今電力電子與再生能源技術快速發展的時代，多電平逆變器（Multilevel Inverter, MLI）因其具備高輸出電壓品質、低諧波失真及低開關損耗等特性，已成為高功率電能轉換應用中不可或缺的關鍵技術。然而，選擇性諧波消除脈波寬度調變（Selective Harmonic Elimination Pulse Width Modulation, SHEPWM）控制策略涉及高度非線性的多重方程求解，使得即時運算與硬體實現面臨挑戰。本論文針對十一階級聯式H橋多電平逆變器（CascadedH-Bridge,CHB-MLI），提出一套結合改良型粒子群演算法（ModifiedParticleSwarmOptimization, MPSO）與深度神經網路（DeepNeuralNetwork,DNN）模型之SHEPWM控制方法。研究首先利用MPSO 求得不同調變指數(ModulationIndex) 下的最優開關角度，作為DNN模型的訓練資料，以實現開關角度預測模型，並以VerilogHDL完成整體硬體架構設計。本文的研究過程以Python進行演算法驗證，後續完成以Cell-based為基礎的完整晶片設計流程，並透過FPGA進行系統驗證。模擬與實驗結果顯示，本方法能有效抑制低次諧波、提升輸出波形品質，並顯著降低濾波器尺寸與運算延遲，展現其於多電平逆變器即時控制應用中的可行性與優勢。;In recent years, multilevel inverters (MLIs) have played a crucial role in modern power electronics and renewable energy systems due to their advantages of high output voltage qual ity, low harmonic distortion, and reduced switching losses. However, the Selective Harmonic Elimination Pulse Width Modulation (SHEPWM) technique involves solving highly nonlin ear transcendental equations, which poses significant challenges for real-time computation and hardware implementation. This thesis focuses on an eleven-level Cascaded H-Bridge Multilevel Inverter (CHB-MLI) and proposes a SHEPWM control method that combines the Modified Particle Swarm Opti mization (MPSO) algorithm with a Deep Neural Network (DNN). The MPSO algorithm is first employed to obtain optimal switching angles under different modulation indices, which are then used to train the DNNmodelforfast, non-iterative prediction of switching angles. The proposed DNN adopts the ReLU and piecewise linear approximation (PLAN) Sigmoid activation func tions, and the overall hardware architecture is implemented using Verilog HDL. Theproposedmethodisverified through algorithm validation in Python, followed by a com plete cell-based chip design flow and FPGA implementation. Simulation and experimental re sults demonstrate that the proposed approach effectively suppresses low-order harmonics, im proves output waveform quality, and significantly reduces filter size and computation latency, proving its feasibility and advantages in real-time multilevel inverter control applications.
顯示於類別:	[電機工程研究所] 博碩士論文

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