| 摘要: | 本研究基於In-Ga-Zn-O(IGZO)為通道之氧化物半導體電晶體(Oxide Semiconductor Field Effect Transistor)，並搭配Hf¬0.5Zr0.5O2(HZO)為結構之鐵電電容(FeCAP)實現計算式的記憶體應用。首先，我們會使用兩顆電晶體加上鐵電電容分別運用於寫入與讀取，其中寫入的電晶體與鐵電電容形成FeRAM ，讀取的電晶體與鐵電電容形成FeFET，藉由這種分開的操作能夠有效的提升真實的寫入跨壓(FeRAM優勢)與保持準非破壞性的功能(FeFET優勢)，同時能夠自由的控制Area Ratio(AR)比例( A_FeCAP/A_transister)與操作電壓的大小來調整鐵電電容與讀取電晶體的分壓，展現出2T1C靈活的運用。在本篇的實驗當中，我們主要比較了4種不同AR比例的特性，分別為AR=1、0.3、0.1、0.03，其中我們是藉由固定A_FeCAP，調整A_transister來完成。
接著，我們使用HSPICE進一步進行電路模擬，其中鐵電電容採用NLS model，電晶體則使用FinFET模型。首先，我們針對單顆鐵電電容的P–V曲線與2T1C的Id–Vg特性進行參數擬合，使模擬行為能與實驗結果一致，確保後續陣列分析的準確性。完成元件層級校正後，我們進一步建立2TnC的電路模型，以評估寫入與讀取時因共線結構所造成的電壓分配與極化變化。透過模擬不同偏壓、時間與路徑條件，可系統性分析非目標FeCAP承受的干擾量，並驗證1S1C(one selector one FeCAP)抑制方法對竄流行為的影響。此外，我們也比較了不同OTS selector材料與不同FeCAP數量在相同操作電壓、時間下的state 1與state 0的區分能力，以判斷其對大陣列行為的適用性。最終，本研究透過一系列的分析，建構出近乎disturb-free系統，做為後續探討記憶體可靠度與電路設計的基礎。
;This study is based on oxide semiconductor field-effect transistors (Oxide Semiconductor FETs) using In-Ga-Zn-O (IGZO) as the channel material, combined with ferroelectric capacitors (FeCAPs) composed of Hf0.5Zr0.5O2 (HZO) to realize a computing-in-memory application. First, we employ two transistors together with one FeCAP, where the write operation is performed by the transistor–FeCAP pair functioning as a FeRAM, and the read operation is carried out by another transistor–FeCAP pair functioning as a FeFET. By separating the write and read paths, the architecture can simultaneously provide a larger effective write voltage (benefit of FeRAM) and maintain quasi-non-destructive readout (benefit of FeFET), while also allowing flexible control of the area ratio (AR = A_FeCAP / A_transistor). This flexibility enables tuning of the voltage division between the FeCAP and the read transistor, demonstrating the versatility of the proposed 2T1C structure. In this work, we experimentally compare four different AR values—AR = 1, 0.3, 0.1, and 0.03—by fixing FeCAP area and adjusting the transistor area accordingly.
Subsequently, HSPICE is used to perform circuit-level simulations, where the FeCAP is modeled using the NLS model and the transistor is modeled using a FinFET device model. We first calibrate the model by fitting the FeCAP P–V curves and the 2T1C Id–Vg characteristics so that the simulated device behavior matches the experimental results, ensuring the accuracy required for array-level analysis. After completing the device-level calibration, we construct a 2TnC circuit model to evaluate the voltage distribution and polarization variation caused by shared-line structures during write and read operations. By simulating various bias conditions, pulse durations, and current paths, we systematically analyze the disturbance experienced by non-selected FeCAPs and verify the effectiveness of disturbance-suppression methods in reducing sneak current. In addition, different OTS selector materials and different numbers of FeCAPs are compared under identical operating voltages and pulse widths to evaluate their capability to distinguish between state 1 and state 0, thereby determining their suitability for large-scale array operation. Ultimately, this study establishes a near disturb-free system through a series of analyses, providing a solid foundation for future research on memory reliability and circuit-level design. |
