| 摘要: | 本論文分別利用tsmcTM 180 nm CMOS及WINTM 120 nm GaN 製程設計寬頻接收機及功率放大器。論文中共有三顆晶片，其中以CMOS製程進行製作的包含C/X頻段寬頻低雜訊放大器與接收機，而Ka頻段高功率的功率放大器以GaN製程來進行設計，而此功率放大器正在製作中，尚未量測。
第一顆電路的第一級為電阻回授式反向器搭配閘極與源極組成的變壓器來達到寬頻的輸入匹配，第二級則使用共源極放大器，輸出匹配採用閘極與汲極組成的變壓器來實現寬頻輸出匹配，並提高增益，同時也在第二級使用電感峰值技術，提升增益平坦度。在輸出匹配網路的設計則以減少損耗，完成輸出功率匹配及改善增益平坦度，並縮小晶片面積，實現應用於C/X頻段的寬頻低雜訊放大器。此電路量測最高增益為13.4 dB，3-dB頻寬從0.8 - 11.5 GHz，最低雜訊指數為2.1 dB，線性度P1dB量測結果為-8 ~ -18.5 dBm，線性度IIP3則為-12 ~ 2 dBm，量測功耗為11.206 mW，晶片面積為0.862 × 0.548 mm^2。
第二顆電路為應用於C/X頻帶寬頻之接收機，整體接收機前端包含四個子電路：第一級為寬頻低雜訊放大器，使用第一顆的寬頻低雜訊放大器，第二級為雙共振點的寬頻巴倫，第三級為雙平衡被動混頻器，第四級則為兩級的轉阻放大器(TIA)。該架構有效提升信號隔離度與增益平坦度，並減少功耗。此電路量測最高轉換增益(Conversion Gain)為26.41 dB，3-dB頻寬從2.8 - 11.8 GHz，最小雙邊帶雜訊指數為4.7 dB，線性度P1dB量測結果為-27.5 ~ -24 dBm，線性度IIP3則為-21 ~ -19 dBm，量測功耗為32.33 mW，晶片面積為1.325 × 0.874 mm^2。
第三顆電路為用於 Ka 頻段寬頻高效率氮化鎵功率放大器，分析了利用最大可用增益與最大穩定增益 (MAG/MSG)、最大震盪頻率 (fmax) 以及最大截止頻率 (fT)的方式，選出最佳電晶體尺寸，達到寬頻高效率和高功率，輸出匹配電路運用連續B類技術，達到寬頻且高效率之功率放大器。模擬結果顯示最佳傳輸增益為20.7 dB，3 dB頻寬為26.6 - 30 GHz，飽和輸出功率為 33.1 dBm，功率附加效率最高可達 31 %，晶片面積為 2.15 × 0.726 mm2。
;This thesis presents the design and development of three integrated circuits using the tsmcTM 180-nm CMOS and WINTM 120-nm GaN processes to design a broadband receiver and a power amplifier, respectively. Three chips included a CMOS-based C/X-band broadband LNA and a C/X-band broadband receiver, and a Ka-band high-power PA implemented in GaN technology.
The first chip is a wideband LNA, which first stage is a resistive-feedback inverter combined with a gate–source transformer to realize broadband input matching. The second stage is a common-source amplifier; the gate-drain transformer in the output network provides broadband output matching while boosting gain. Inductive peaking is further applied at the second stage to flatten gain. The output matching thus reduces power consumption, improves output match and gain flatness, and shrinks chip area. Measured results show a peak gain of 13.4 dB, a 3-dB bandwidth from 0.8 to 11.5 GHz, a minimum NF of 2.1 dB, a P1dB between -18.5 and -8 dBm, an IIP3 between -12 and 2 dBm, with a power consumption of 11.206 mW. The chip area is 0.862 × 0.548 mm².
The second chip is a wideband receiver, which comprises four blocks including a broadband LNA integrated previous LNA from Chip 1, a dual-resonance broadband balun, a double-balanced passive mixer, and a two-stage TIA. This architecture enhances signal isolation and gain flatness while reducing power consumption. Measured results achieve a peak conversion gain of 26.41 dB over a 3-dB bandwidth from 2.8 to 11.8 GHz, a minimum DSB NF of 4.7 dB. The measured P1dB is between -27.5 and -24 dBm, IIP3 is between -21 and -19 dBm. Total power consumption is 32.33 mW. The chip area is 1.325 × 0.874 mm².
The third chip is a Ka band broadband high efficiency power amplifier in GaN process. Transistor sizing is determined through MAG/MSG, fmax, and fT to achieve wideband, high-efficiency, and high-power performance. The output matching network adopts a Class-B continuous-mode technique to realize a broadband, high efficiency PA. Simulation results show that the peak gain is 20.7 dB, the 3-dB bandwidth is from 26.6 to 30 GHz, the saturated output power is 33.1 dBm, the peak power added efficiency (PAE) is up to 31%. The chip area is 2.15 × 0.726 mm². |
