6 吋矽基板上沉積1700 V 氮化鎵高電子遷移率電晶體之緩衝層研究;Buffer Layer Design toward 1700 V GaN HEMTs on 6-inch Si Substrates

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題名:	6 吋矽基板上沉積1700 V 氮化鎵高電子遷移率電晶體之緩衝層研究;Buffer Layer Design toward 1700 V GaN HEMTs on 6-inch Si Substrates
作者:	徐紹翔;Hsiang, Hsu Shao
貢獻者:	電機工程學系
關鍵詞:	氮化鎵高電子移動率電晶體;功率元件;磊晶;超晶格;GaN HEMT;Power Device;Epitaxy;Superlattice
日期:	2026-01-14
上傳時間:	2026-03-06 18:58:16 (UTC+8)
出版者:	國立中央大學
摘要:	本研究主要探討在6吋矽基板上沉積1700 V 氮化鎵高電子遷移率電晶體之緩衝層設計，用於高崩潰電壓應用中，其磊晶緩衝層之超晶格結構設計與成長之影響。隨著功率電子元件朝向更高電壓、更高效率的方向發展，如何在受限的 GaN-on-Si 磊晶厚度下有效抑制垂直方向漏電流並提升崩潰電壓，是目前業界與學界的核心挑戰。本研究即針對不同超晶格結構之材料組成、厚度與堆疊方式進行模擬與實驗分析，旨在建立高崩潰電壓緩衝層之最佳化設計準則。本論文首先利用MATLAB之傳輸矩陣法（TMM）模擬電子穿隧行為，並以高能區域之反射率積分面積作為比較指標，分析不同超晶格結構（標準超晶格與複合式超晶格）對電子傳輸的影響。模擬顯示反射率面積受能障差（ΔEc）影響。根據模擬結果，本研究實際成長多組超晶格樣品，並以垂直崩潰電壓量測驗證其結構與電性差異。實驗結果顯示，提升超晶格總厚度可增加崩潰電壓，平均每增加1 nm的超晶格可帶來約0.4–0.48 V 的崩潰電壓提升。然而隨厚度增加，其改善幅度逐漸趨緩，顯示需在厚度與結構設計間取得平衡。本研究提出之複合式超晶格結構，透過調整其週期性配置與材料比例，在維持較高等效鋁含量的同時，仍具良好的反射率面積表現。最終所提出的最佳化結構可實現最大1855 V的垂直崩潰電壓，漏電流低1 A/cm²，且在高電場區域之漏電流斜率較傳統結構改善約 10%。此外，本論文亦探討高厚度磊晶結構之翹曲問題，並透過調整緩衝層設計有效降低基板破裂風險。綜合來看，本研究成功提升超晶格結構緩衝層之高壓特性，並提供磊晶層最佳化之具體指引，對未來開發高崩潰電壓、高可靠度之GaN功率元件具有重要參考價值。;This study investigates the buffer layer design for 1700 V GaN HEMTs grown on 6-inch substrates, focusing on the impact of superlattice structures on high breakdown voltage applications. As power electronic devices advance toward higher voltage and efficiency, effectively suppressing vertical leakage current and enhancing breakdown voltage within the limited GaN-on-Si epitaxial thickness has become a central challenge for both industry and academia. This work analyzes different superlattice structures—considering material composition, thickness, and stacking configuration—through simulation and experimental validation, aiming to establish optimized design guidelines for high-voltage buffer layers. First, the transmission matrix method (TMM) in MATLAB was employed to simulate electron tunneling behavior. The integrated reflectance area in the high-energy region was used as a comparative metric to evaluate the influence of different superlattice structures (standard and composite superlattices) on electron transport. Simulation results revealed that the reflectance area is strongly affected by the conduction band offset (ΔEc). Based on these findings, multiple superlattice samples were grown and characterized through vertical breakdown voltage measurements to verify structural and electrical differences. Experimental results demonstrated that increasing the total superlattice thickness effectively enhances breakdown voltage, with an average improvement of approximately 0.4–0.48 V per additional nanometer. However, the enhancement gradually saturates with increasing thickness, indicating the need to balance thickness and structural design. The proposed composite superlattice structure, achieved by adjusting periodic configuration and material ratios, maintains a relatively high effective aluminum content while exhibiting favorable reflectance performance. The optimized structure ultimately achieved a maximum vertical breakdown voltage of 1855 V, with leakage current below 1 A/cm², and demonstrated a ~10% improvement in leakage current slope under high electric fields compared to conventional structures. In addition, this study addressed wafer bowing issues associated with thick epitaxial layers and showed that buffer layer design adjustments can effectively reduce substrate fracture risk. ii In summary, this work successfully enhances the high-voltage characteristics of superlattice buffer layers and provides concrete optimization guidelines for epitaxial design. These findings offer valuable insights for the future development of high-breakdown-voltage, high-reliability GaN power devices.
顯示於類別:	[電機工程研究所] 博碩士論文

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