| 摘要: | 本研究針對p型閘極氮化鎵高電子遷移率電晶體（p-GaN gate HEMT）之閘極結構設計進行探討，重點在於不同p-GaN覆蓋層結構對元件直流特性、動態特性、電容行為與崩潰特性之影響。為改善鎂摻雜分布問題，本研究製作四種不同p-GaN結構的樣品：（A）單層p-GaN、（B）p-GaN + UID-GaN、（C）雙層p-GaN、（D）雙層p-GaN + UID-GaN。
SIMS量測結果顯示，UID-GaN夾層能有效抑制鎂向下擴散，而雙層濃度的p-GaN結構可使p-GaN層內的鎂濃度分布更為均勻。直流特性方面，相較於單層與雙層p-GaN結構，含UID-GaN且具雙層p-GaN的樣品D具有最低導通電阻（2.5 Ω·mm）及較高的閾值電壓（0.6 V）。在動態量測中，樣品D的Drain lag明顯改善，電流崩塌率降低約10 %，動態導通電減少約1.8倍。
電容特性分析指出，樣品D於金屬/p-GaN接面具有較大的接面電容，且平帶電壓相較樣品B右移約0.7 V，反映其較佳的鎂分布均勻性。同時，介面能態密度（Dit）落在0.47 × 1012 ~ 1.57 × 1012 cm-2·eV-1，顯示UID-GaN 能有效減少鎂摻雜造成的介面缺陷。崩潰特性方面，元件具有超過60 V的截止崩潰電壓與11.6 V的閘極崩潰電壓，適合應用於低壓功率轉換器。
綜合上述結果，本研究證實了「雙層 p-GaN」搭配「UID-GaN夾層」的結構能同時改善導通電阻、閾值電壓、動態特性與崩潰特性，是提升E-mode GaN HEMT整體特性的重要設計方向。
;This study investigates the gate-stack design of p-GaN gate high-electron-mobility transistors (HEMTs), focusing on how different p-GaN cap structures influence the device’s DC characteristics, dynamic behavior, capacitance response, and breakdown performance. To address the issue of Mg diffusion and non-uniform doping, four types of p-GaN cap structures were fabricated: (A) single-layer p-GaN, (B) p-GaN with a UID-GaN interlayer, (C) dual-level p-GaN, and (D) dual-level p-GaN combined with a UID-GaN interlayer.
SIMS analysis confirms that the UID-GaN interlayer effectively suppresses downward Mg diffusion, while the dual-level p-GaN structure leads to a more uniform Mg concentration profile. In the DC characteristics, sample D—containing both the dual-level p-GaN and UID-GaN interlayer—exhibits the lowest on-resistance (2.5 Ω·mm) and a higher threshold voltage (0.6 V) compared with the other structures. Dynamic measurements further show that sample D demonstrates a significantly reduced drain lag, with the current collapse ratio improved by approximately 10 % and the dynamic on-resistance reduced by a factor of 1.8.
Capacitance analysis reveals that sample D exhibits a larger metal/p-GaN junction capacitance and a 0.7 V rightward shift in flat-band voltage relative to sample B, reflecting its enhanced doping uniformity. The interface state density (Dit), ranging from 0.47 × 10¹² to 1.57 × 10¹² cm⁻²·eV⁻¹, indicates that the UID-GaN interlayer effectively reduces Mg-related interface defects. Regarding breakdown characteristics, the devices achieve an off-state breakdown voltage exceeding 60 V and a gate breakdown voltage above 11.6 V, making them well-suited for low-voltage power conversion applications.
Overall, this work demonstrates that combining a dual-level p-GaN structure with a UID-GaN interlayer simultaneously improves on-resistance, threshold voltage, dynamic performance, and breakdown robustness, establishing it as a promising design strategy for enhancing the performance of E-mode GaN HEMTs. |
