| 摘要: | 本研究以低壓p型氮化鎵閘極高電子遷移率電晶體為研究對象，探討p-GaN厚度調控以及不同閘極絕緣層之金屬-絕緣層-p型氮化鎵閘極結構，對元件直流特性、崩潰行為與動態可靠度之影響，以釐清低壓增強型p-GaN閘極元件之關鍵結構與製程因素。
研究中包含Silvaco TCAD模擬與實際元件製作，首先比較不同p-GaN厚度之蕭特基p-GaN gate HEMT，結果顯示，隨著p-GaN厚度增加，元件臨界電壓呈現正向偏移，顯示閘極對通道之控制能力提升；然而，部分厚p-GaN元件亦伴隨次臨界特性劣化及較高之閘極漏電流，且於變溫量測下其穩定性受到影響，顯示p-GaN厚度設計需在臨界電壓調控與電場分佈之間取得平衡。此外，動態量測結果指出，p-GaN閘極元件於負閘極偏壓應力後會產生電性退化，且尺寸較小之元件退化現象更為明顯。
進一步於p-GaN閘極中分別引入氮化矽及氧化鋁作為閘極絕緣層，形成MIS p-GaN gate HEMT結構，結果顯示，MIS p-GaN結構可有效抑制正向閘極偏壓下之漏電流，並擴大閘極操作電壓範圍。本研究中氮化矽MIS p-GaN元件展現較佳之漏電流抑制效果，但同時有明顯之臨界電壓偏移與介面電荷效應；氧化鋁MIS p-GaN元件透過TMA前處理可改善介面穩定性並降低轉移特性遲滯現象，但其臨界電壓多呈現負向偏移。針對氧化鋁介電層，本研究進一步比較不同製程流程，結果顯示介電層沉積順序與歐姆接觸區處理方式，對導通能力與臨界電壓表現具有顯著影響。
在可靠度分析方面，動態量測與電容—電壓分析結果顯示，元件動態退化行為與閘極絕緣層材料及其介面缺陷密度密切相關，而介電層/AlGaN介面之缺陷特性高度依賴製程條件。整體而言，本研究指出低壓p-GaN gate HEMT及MIS p-GaN gate HEMT之電性與可靠度需同時考量p-GaN厚度設計、元件尺寸效應與閘極堆疊介面品質。;This study investigates low-voltage p-type gallium nitride (p-GaN) gate high-electron-mobility transistors (HEMTs), focusing on the effects of p-GaN thickness modulation and metal-insulator-p-GaN (MIS p-GaN) gate structures with different gate dielectrics on the DC characteristics, breakdown behavior, and dynamic reliability of the devices. The target is to clarify the key structural and process-related factors affecting low-voltage enhancement-mode p-GaN gate devices.
The study includes Silvaco TCAD simulation and experimental device fabrication. First, Schottky p-GaN gate HEMTs with different p-GaN thicknesses are compared. The results show that increasing the p-GaN thickness leads to a positive shift in threshold voltage, indicating enhanced gate control over the channel. However, most of the devices with thicker p-GaN layers exhibit degraded subthreshold swing, increased gate leakage current, and reduced stability under temperature-dependent measurements, indicating that p-GaN thickness design requires a trade-off between threshold voltage control and electric-field distribution. In addition, dynamic measurements reveal that p-GaN gate devices experience electrical degradation after negative gate-bias stress, with more significant degradation observed in devices with smaller dimensions.
Furthermore, silicon nitride and aluminum oxide are added as gate dielectrics in the p-GaN gate structure to form MIS p-GaN gate HEMTs. The results demonstrate that the MIS p-GaN structure effectively suppresses gate leakage current under forward gate bias and expands the gate swing. In this study, silicon nitride MIS p-GaN gate devices exhibit superior leakage suppression capability but also show significant threshold voltage shift and interface charge accumulation. Aluminum oxide MIS p-GaN gate devices, with TMA pretreatment, show improved interface stability and reduced hysteresis in transfer characteristics, although their threshold voltages tend to shift in the negative direction. For aluminum oxide gate dielectrics, different process flows are further compared, revealing that the dielectric deposition sequence and the treatment of the ohmic contact region have significant impacts on conduction capability and threshold voltage.
Dynamic measurements and capacitance–voltage analysis indicate that device degradation is strongly correlated with the gate dielectric material and its interface state density, while defect characteristics at the dielectric/AlGaN interface are highly dependent on process conditions. Overall, this study demonstrates that the electrical performance and reliability of low-voltage p-GaN gate HEMTs and MIS p-GaN gate HEMTs must be considered together with p-GaN thickness design, device scaling effects, and gate stack interface quality. |
