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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/99445


    題名: 微型化雙頻平衡式與可重組式 功率分配器設計;Miniaturized Dual-Band Balanced and Reconfigurable Power Divider Design
    作者: 闕孟平;Chueh, Meng-Ping
    貢獻者: 電機工程學系
    關鍵詞: 微型化;功率分配器;雙頻橋式T線圈;可重組式;平衡式
    日期: 2026-01-19
    上傳時間: 2026-03-06 19:00:39 (UTC+8)
    出版者: 國立中央大學
    摘要: 本論文以微型化雙頻平衡式功率分配器與可重組式功率分配器為研究目標,提出具吸收共模雜訊效果的雙頻平衡式功率分配器、可實現不同功率分配比的雙頻平衡式功率分配器,以及整合功率分配器與射頻開關兩種功能的可重組式的功率分配器。設計上使用雙頻橋式T線圈(Bridged T-Coil, BTC)取代傳輸線,同時達到電路尺寸微型化與雙頻操作的效果,從而大幅簡化雙頻微波被動電路的設計複雜度。
    首先,以WIPD製程實現之10/24 GHz吸收式雙頻平衡式功率分配器,可吸收輸入端的共模雜訊,其電路面積為3.829 mm × 2.605 mm,在兩中心頻率之電氣尺寸分別為0.1270 × 0.0860與0.30 × 0.210。其次,以90-nm CMOS製程實現之10.7/20 GHz雙頻不等分平衡式功率分配器,其電路面積為1.08 mm × 1.29 mm,在兩中心頻率之電氣尺寸分別為0.0380 × 0.0460與0.0720 × 0.0860。兩個雙頻平衡式功率分配器的電路面積皆遠小於既有文獻,成功達成微型化的設計目標。
    最後,為因應切換式波束成型系統之應用需求,本研究以GaN12製程實現2.45/5.8 GHz雙頻可重組式功率分配器,此電路可於單刀雙擲開關與功率分配器兩種工作模式間切換,並成功達成雙頻操作效果,其電路面積為2.667 mm × 1.831 mm,在兩中心頻率之電氣尺寸分別為0.02180 × 0.01490與0.05160 × 0.03540。
    ;This thesis focuses on the design of miniaturized dual-band balanced power dividers and reconfigurable power dividers. Specifically, a dual-band balanced power divider capable of common-mode noise absorption, a dual-band balanced power divider with unequal power division ratio, and a reconfigurable power divider that integrates the functions of power divider and RF switch are proposed. In these designs, dual-band bridged T-coils are used to replace transmission lines to simultaneously achieve circuit miniaturization and dual-band operation, which greatly simplifies the design of dual-band microwave passive components.
    First, the proposed 10/24 GHz dual-band absorptive balanced power divider is implemented using the WIPD process, and it successfully achieves the absorption of input common-mode noise. The circuit size is only 3.829 mm × 2.605 mm, while the corresponding electrical sizes are 0.1270 × 0.0860 at 10 GHz and 0.30 × 0.210 at 24 GHz. Next, a 10.7/20 GHz dual-band balanced power divider with unequal power division ratio is implemented using a 90-nm CMOS process. The circuit size is 2.38 mm × 1.9 mm. The corresponding electrical sizes at 10.7 and 20 GHz are 0.0380×0.0460 and 0.0720×0.0860, respectively. The circuit sizes of them are much smaller than those reported in existing literature, and the goal of circuit size miniaturization is successfully achieved.
    Finally, targeting for switched beamforming system applications, a 2.45/5.8 GHz dual-band reconfigurable power divider is implemented using the GaN12 process. It can be switched between the single-pole double-throw switch mode and the power divider mode, while the desired dual-band operation is also achieved. The circuit area is 2.667 mm × 1.831 mm, and the corresponding electrical sizes are 0.02180×0.01490 at 2.45 GHz and 0.05160×0.03540 at 5.8 GHz.
    顯示於類別:[電機工程研究所] 博碩士論文

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