| 摘要: | 實體設計（physical design, PD）是現代超大型積體電路（very-large-scale integration, VLSI）設計流程中至關重要的階段，顯著影響積體電路的效能、功耗與面積（power, performance, and area, PPA）。在實體設計的眾多步驟中，擺置（placement）十分關鍵，因為其決定了元件的空間分布，並直接影響後續繞線（routing）的效率與品質。然而，繞線階段極具複雜性，需同時優化時序、壅塞及繞線資源分配。在實務上，常需要透過頻繁的拆線重繞（rip-up and reroute, RR）以解決設計規則違反（design rule violations, DRVs）與時序違反（timing violations），導致設計週期冗長並且阻礙設計收斂。因此，在擺置階段準確預測細部繞線的線長（detailed routed wirelength, DRWL），對於提升時序可預測性與緩解壅塞問題是十分重要的。此類預測能力可減少擺置與繞線階段間的反覆修正，進而加速設計收斂。
傳統的線長估計技術，例如半周長線長（half-perimeter wire length, HPWL）與基於直角史坦納最小樹（rectilinear Steiner minimum tree, RSMT）的模型，雖分別具備良好計算效率或較佳的幾何擬合度，但往往無法充分捕捉實際繞線情境中因壅塞或繞道造成的偏差。隨著機器學習（Machine Learning, ML）技術的快速發展，近年來已有研究嘗試以機器學習模型進行線長預測。然而，多數方法存在以下限制：一是僅能預測總線長或估計線長，像是半周長線長或是基於直角史坦納最小樹，而非個別繞線層級（net-level）的實際繞線線長；二是依賴複雜的深度學習架構，需複雜特徵與高運算成本，使得模型在推論（inference）階段耗費大量運算資源，限制其在工業實際設計流程中的應用。
為解決上述限制，本研究提出一種基於機器學習的輕量化線長預測架構，利用擺置階段取得的特徵，預測個別繞線（per-net）的細部繞線線長。相較於僅能估算總線長或依賴高計算成本模型的既有方法，本研究採用線性回歸（linear regression）模型，僅需低運算複雜度，就能實現精確的個別繞線層級預測。此外，我們引入與壅塞相關的關鍵特徵，例如矩形均勻線密度（rectangular uniform wire density, RUDY），以進一步提升預測準確性。
在 ISPD 2015基準測試集上的實驗結果顯示，本研究方法在預測準確度上優於傳統HPWL基準，其均方根誤差（root mean square error, RMSE）與均方誤差（mean square error, MSE）分別平均降低6.44%與8.58%。本方法具備高計算效率與良好的可擴充性，展現了與現有擺置工具整合的潛力，能有效加速設計收斂。本研究為擺置階段的線長預測提供了一項具實用性且有效的解決方案，在現代VLSI實體設計流程中實現了準確性及穩健性的良好平衡。
;Physical design is a crucial stage in modern very-large-scale integration (VLSI) design flows, significantly impacting the power, performance, and area (PPA) of the integrated circuits. Among the various stages, placement is particularly pivotal, as it dictates the spatial distribution of components and directly influences the efficiency and quality of subsequent routing. However, routing is inherently complex, requiring the simultaneous optimization of timing, congestion, and routing resource allocation. In practice, frequent rip-up and reroute (RR) iterations are often necessary to resolve design rule violations (DRVs) and timing violations, which prolong the design cycles and hinder design closure. Therefore, accurately predicting detailed routed wirelength (DRWL) during the placement stage is essential for enhancing timing predictability and alleviating congestion. Such predictive capabilities can minimize the iterations between placement and routing, thereby accelerating design convergence.
Traditional wirelength estimation techniques, such as half-perimeter wire length (HPWL) and rectilinear Steiner minimum tree (RSMT)-based models, offer computational efficiency or geometric accuracy but often fail to capture deviations caused by routing detours and congestion in real routing scenarios. With the rapid advancement of machine learning (ML), several recent studies have explored ML-based approaches for wirelength prediction. However, most existing methods either predict only total wirelength or estimate simplified wirelength, such as HPWL or RSMT, rather than actual per-net routed wirelength at the net level, and often rely on complex deep learning architectures that require numerous features and incur high computational overhead, leading to long inference times and limiting their applicability in industrial physical design flows.
To address these limitations, this research proposes a lightweight ML-based wirelength prediction framework that utilizes features obtained from the placement stage to predict per-net DRWL . Unlike prior methods that estimate only total wirelength or depend on computationally expensive models, the proposed method employs a linear regression model to achieve accurate per-net predictions while maintaining low computational complexity. Additionally, we incorporate key congestion-related features, such as rectangular uniform wire density (RUDY), to further enhance prediction accuracy.
Experimental results on the ISPD 2015 benchmark suite demonstrate that the proposed method outperforms the traditional HPWL-based baseline, achieving average reductions of 6.44% and 8.58% in root mean square error (RMSE) and mean square error (MSE), respectively. The approach exhibits high computational efficiency and scalability, offering significant potential for integration with existing placement tools to accelerate design convergence. This work provides a practical and effective solution for placement-stage wirelength prediction, striking a favorable balance between accuracy and robustness for modern VLSI physical design flows. |
