模組擺置為超大型積體電路（Very-Large-Scale Integration, VLSI）實體設計中極為關鍵的階段之一，預先設計之模組擺放位置將直接影響線長、繞線擁塞以及整體晶片效能。近年來，基於強化學習（Reinforcement Learning, RL）的擺置方法在自動化模組擺置方面展現出相當潛力，然而現有方法仍普遍面臨收斂速度緩慢、異質資訊整合困難，以及在不同電路設計間泛化能力不足等問題，進而限制其於實務設計流程中的應用。 為解決上述挑戰，本論文提出一種基於強化學習進行模組擺置的方法，透過輕量化的多模型特徵融合機制，整合電路連線結構資訊與晶片擺置空間資訊，使擺置決策能在兼顧效能與模型效率的情況下更為精準。此外，本研究引入強化的輸入影像式表示方法，為訓練過程提供結構化且具判別力的空間資訊，並能夠採用多電路訓練策略，在不依賴預先擺置資料或監督式預訓練的前提下，實現良好的泛化能力。 在 14 個真實工業級測資與 4 個公開基準測資上的實驗結果顯示，相較於既有的強化學習式擺置方法，本研究所提出的方法可達成約 5% 至 55% 的線長改善，並於訓練與推論效率上平均提升約 3 倍。在提升模型適應性、訓練效率與可擴展性的同時，本方法為現代超大型積體電路實體設計中的巨集模組擺置問題提供了一項具實用性且有效的解決方案。 ;Placement plays a vital role in the physical design stage of very-large-scale integration (VLSI) systems, where the placement of pre-designed functional blocks has a significant impact on wirelength, routing congestion, and overall chip performance. Although recent reinforcement learning (RL)-based approaches have demonstrated promising potential for automating the placement process, they often suffer from slow convergence, difficulties in effectively integrating heterogeneous sources of information, and limited generalization across different circuit designs. These limitations hinder their practical adoption in real-world design flows. To address these challenges, this thesis proposes a novel RL-based placement framework that jointly integrates global netlist connectivity and local layout context through a lightweight multimodal feature fusion mechanism. This design enables the agent to make informed placement decisions while maintaining computational efficiency. In addition, the proposed placer employs enriched image-based layout representations to provide structured spatial guidance during training and adopts a multi-circuit training strategy that facilitates robust generalization without relying on expert placement data or supervised pretraining. Experimental results on 14 industrial-grade benchmarks and 4 public benchmarks demonstrate that the proposed approach achieves wirelength reductions ranging from 5% to 55% compared to existing RL-based methods. Moreover, the framework improves average training and inference efficiency by up to 3× while maintaining competitive placement quality. By enhancing adaptability, training efficiency, and scalability, the proposed method provides a practical and effective solution for placement in modern VLSI physical design.
