硼在氮化鎵高電子遷移率電晶體中的應用與影響;The Applications and Impacts of Boron in Gallium Nitride High Electron Mobility Transistors

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題名:	硼在氮化鎵高電子遷移率電晶體中的應用與影響;The Applications and Impacts of Boron in Gallium Nitride High Electron Mobility Transistors
作者:	林宏洋;Lin, Hung-Yang
貢獻者:	電機工程學系
關鍵詞:	氮化鎵;高電子遷移率電晶體;硼;GaN;HEMT;MOSFET
日期:	2026-01-28
上傳時間:	2026-03-06 19:02:22 (UTC+8)
出版者:	國立中央大學
摘要:	本論文研究專注在有機金屬化學氣相沉積系統(MOCVD)成長氮化鎵高電子遷移率電晶體(GaN HEMT transistor)於低阻(111)矽基板上。本研究突破過去僅以碳(Carbon)或鐵(Iron)摻雜在氮化鎵緩衝層的方式，提出將硼摻雜在氮化鎵緩衝層，並發現以傳統連續成長的方式會造成成長模式由原先的Stranski–Krastanov (SK) 模式轉變為 Volmer–Weber (VW) 島狀成長並發生品質劣化的問題。故我們提出delta doping的摻雜方式將硼在不改變理想模式的情況下加入1200 V高功率結構的GaN緩衝層中，引入10對單原子層高濃度硼摻雜。實驗結果顯示，當崩潰電流密度定義為0.1 A/cm2時，崩潰電壓則由參考樣品的398 V顯著提升至975 V。另外在氮化硼鎵下位障層(BGaN back barrier)研究方面，首次將足夠厚的氮化硼鎵下位障層引入高電子遷移率電晶體中，並成功優化理想成長條件為12 nm的 B0.015Ga0.985N，補足過去在理論模擬與實際元件應用之間的差距。在元件表現上，相對於參考樣品，引入下位障層後，臨界電壓從1.7 V上升至2.1 V，Ion/Ioff ratio由3.21×108上升至1.27×109，VG = -3時閘極漏電流(IG)由5.927×10-7 mA/mm下降至7.54×10-8 mA/mm，垂直崩潰電壓由1210 V 提升至1275 V ; 在 Drain lag 量測中，動態導通電阻僅上升至 1.7 倍，且水平方向崩潰電壓最高可達 1491 V 並伴隨較低漏電流斜率，證實BGaN下位障層設計具有高阻值特性與提升載子侷限性能力。;This thesis focuses on the growth of GaN high electron mobility tran-sistors (HEMTs) on low resistivity (111) Si substrates by metal organic chemical vapor deposition (MOCVD). Beyond the conventional approach of employing carbon or iron doping in the GaN buffer, we propose the incor-poration of boron into the GaN buffer layer. However, it is found that con-ventional continuous growth leads to a transition of the growth mode from the Stranski–Krastanov (SK) mode to a Volmer–Weber (VW) island growth mode, resulting in degraded crystalline quality. To address this issue, a boron delta doping scheme is introduced into the GaN buffer of a 1200 V high-power structure, where 10 pairs of monolayer level, heavily bo-ron-doped layers are embedded without disturbing the desired growth mode. Experimental results show that, under a breakdown current density criterion of 0.1 A/cm², the breakdown voltage is significantly enhanced from 398 V in the reference sample to 975 V. For the BGaN back barrier (BGaN BB) study, a sufficiently thick BGaN back barrier is incorporated for the first time into a HEMT structure, and the optimal growth condition is identified as a 12 nm thick B0.015Ga0.985N layer, thereby helping to bridge the gap between previous theoretical simulations and practical device implementation. In terms of device performance, compared with the reference sample, the introduction of the BGaN back barrier increases the threshold voltage from 1.7 V to 2.1 V and improves the Ion/Ioff ratio from 3.21×108 to 1.27×109. The gate leakage current IG at VG = −3 V is reduced from 5.927×10-7 mA/mm to 7.54×10-8 mA/mm, while the vertical breakdown voltage is enhanced from 1210 V to 1275 V. In Drain lag measurement, the dynamic on-resistance increases only to 1.7 times its static value, and the lateral breakdown voltage reaches as high as 1491 V with a reduced leakage current slope, confirming the high resistivity of the BGaN layer and its effectiveness in strengthening carrier confinement.
顯示於類別:	[電機工程研究所] 博碩士論文

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