高性能嵌入式聯網視覺系統

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姓名

黃柏軒(Po-Hsuan Huang) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

高性能嵌入式聯網視覺系統
(A High Performance Embedded Networking Vision System)

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摘要(中)

基於工業檢測和視訊監控對於高解析度影像串流網路的需求，本研究設計了一個高性能的嵌入式聯網視覺系統，整合取像控制、影像處理引擎和Gigabit聯網模組三大子系統。其中Gigabit聯網模組又區分為UDP/IP卸載引擎和低密度奇偶校驗碼(LDPC)兩個子模組。
影像處理引擎的嵌入式硬體實現包含多個高速型態學影像處理電路單元和一個上層的管線化控制器。在影像串流傳輸採用硬體化的Gigabit UDP/IP卸載引擎，結合低密度奇偶校驗碼以提供高可靠度的高速網路串流服務。
本研究以FPGA驗證嵌入式聯網視覺系統，影像處理電路可以運行在125MHz系統時脈，可以處理30 fps Full HD畫質的影像，至於UDP/IP卸載引擎和LDPC均實現Gbps以上的吞吐量。實驗顯示，本系統可以達到傳輸每秒30張無壓縮的VGA解析度影像串流，提供一個低成本、高效能的聯網嵌入式視覺解決方案。

摘要(英)

For the demand of high resolution video streaming networks in the field of industrial inspection and video surveillance, we designed a high-performance embedded networking vision system, which is the integration of image capture control, image processing engine and Gigabit networking module. The Gigabit networking module is even divided into two sub-modules, which are UDP / IP offloading engine and low-density parity-check (LDPC) code.
The hardware implementation of the image processing engine includes multiple high-speed morphological image processing units and an upper pipeline controller. In video streaming transmission, a hardware Gigabit UDP / IP offloading engine is applied and an LDPC code is combined in to provide a highly reliable high-speed Internet streaming services.
This proposed embedded networked vision system is verified by FPGA. The image processing circuit can run up to 125MHz of the system clock with the input 30 fps Full HD quality video. For the UDP / IP offloading engine and LDPC code can both achieve up to Gbps of throughput. Experiments show that our system can achieve the transfer of 30 fps in uncompressed VGA resolution video streams and provides a good networked embedded vision solution with low-cost and high-performance.

關鍵字(中)

★ 嵌入式系統
★ 視覺系統

關鍵字(英)

★ Embedded System
★ Vision System

論文目次

摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章、緒論 1
1.1 研究背景 1
1.2 研究目標 3
1.3 論文架構 3
第二章、文獻回顧 5
2.1 影像處理 5
2.2 資料傳輸 7
2.2.1 PCI Express 8
2.2.2 SATA 8
2.2.3 USB 10
2.2.4 乙太網路 11
2.3 錯誤更正碼 14
2.3.1 BCH code 15
2.3.2 Reed–Solomon code 17
2.3.3 Low-density parity-check code 18
第三章、系統設計 22
3.1 影像處理 22
3.1.1擴張（Dilation）與侵蝕（Erosion） 22
3.1.2斷開（Opening）與閉合（Closing） 23
3.1.3邊緣偵測（Edge Detection） 24
3.1.4銳利化（Sharpening） 25
3.1.5細線化與骨架抽取 27
3.2 乙太網路封包 29
3.3 QC-LDPC 32
3.3.1 編碼器 32
3.3.2 解碼器 34
第四章、嵌入式聯網視覺系統 38
4.1系統架構 38
4.2相機取像子系統 38
4.3影像處理子系統 40
4.4 乙太網路子系統 45
第五章系統實驗 50
5.1 實驗環境 50
5.2系統模組驗證 50
5.3實驗一單一視覺系統功能驗證 55
5.4實驗二多系統驗證 57
第六章結論 58
參考文獻 60

參考文獻

[1] R. C. Gonzalez and R. E. Woods, Digital Image Processing: Addison-Wesley Publishing Company, 1989.
[2] H. Pottmann, S. Leopoldseder, A. Hofer, T. Steiner, and W. Wang, “Industrial geometry: recent advances and applications in CAD,” Computer-Aided Design, vol. 37, pp. 751-766, Jun 2005.
[3] C. C. Han, H. Y. M. Liao, G. J. Yu, and L. H. Chen, “Fast face detection via morphology-based pre-processing,” Pattern Recognition, vol. 33, pp. 1701-1712, Oct 2000.
[4] Q. J. Zhao, W. C. Xu, Y. X. Wang, and X. M. Shi, “Using head poses to control a virtual robot walking in a virtual maze,” Optics Communications, vol. 295, pp. 84-91, May 15 2013.
[5] J. Wang and Z. J. Xu, “STV-based video feature processing for action recognition,” Signal Processing, vol. 93, pp. 2151-2168, Aug 2013.
[6] M. Karkoub, M. G. Her, C. C. Huang, C. C. Lin, and C. H. Lin, “Design of a wireless remote monitoring and object tracking robot,” Robotics and Autonomous Systems, vol. 60, pp. 133-142, Feb 2012.
[7] H. Duan, Y. Fang, and B. M. Huang, “Parallel design of JPEG-LS encoder on graphics processing units,” Journal of Applied Remote Sensing, vol. 6, Sep 11 2012.
[8] N. G. Shankar and Z. W. Zhong, “Improved segmentation of semiconductor defects using area sieves,” Machine Vision and Applications, vol. 17, pp. 1-7, Apr 2006.
[9] S. Y. Chien and L. G. Chen, “Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation,” Journal of Signal Processing Systems for Signal Image and Video Technology, vol. 62, pp. 77-96, Jan 2011.
[10] G. Manduchi, A. Barbalace, A. Luchetta, A. Soppelsa, C. Taliercio, and E. Zampiva, “Upgrade of the RFX-mod real time control system,” Fusion Engineering and Design, vol. 87, pp. 1907-1911, Dec 2012.
[11] H. Lakdawala, M. Schaecher, C. T. Fu, R. Limaye, J. Duster, Y. L. Tan, A. Balankutty, E. Alpman, C. C. Lee, K. M. Nguyen, H. J. Lee, A. Ravi, S. Suzuki, B. R. Carlton, H. S. Kim, M. Verhelst, S. Pellerano, T. Kim, S. Venkatesan, D. Srivastava, P. Vandervoorn, J. Rizk, C. H. Jan, S. Ramamurthy, R. Yavatkar, and K. Soumyanath, “A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 91-103, Jan 2013.
[12] A. Arfan, Y. J. Kim, and J. B. Kwon, “Access time-aware cache algorithm for SATA hard disks,” IEICE Electronics Express, vol. 9, pp. 1707-1713, 2012.
[13] S. Branigan, “Characteristics of Forensic Imaging Performance-An Analysis of Forensic Imaging Bottlenecks,” Journal of Forensic Sciences, vol. 58, pp. 645-650, May 2013.
[14] W. J. Shyr and C. M. Lin, “Developing a Novel USB-PLC Controller for a Mechatronics Cloud Laboratory,” International Journal of Advanced Robotic Systems, vol. 10, Apr 10 2013.
[15] J. M. Ramirez-Cortes, P. Gomez-Gil, V. Alarcon-Aquino, J. Martinez-Carballido, and E. Morales-Flores, “FPGA-based educational platform for real-time image processing experiments,” Computer Applications in Engineering Education, vol. 21, pp. 193-201, Mar 2013.
[16] G. Parsons, “Ethernet bridging architecture,” IEEE Communications Magazine, vol. 45, pp. 112-119, Dec 2007.
[17] K. Tanaka, A. Agata, and Y. Horiuchi, “IEEE 802.3av 10G-EPON Standardization and Its Research and Development Status,” Journal of Lightwave Technology, vol. 28, pp. 651-661, Feb 15 2010.
[18] C. E. Shannon, “A Mathematical Theory of Communication,” Bell System Technical Journal, vol. 27, pp. 379-423, 623-656, 1948.
[19] J. Cho and W. Sung, “Efficient Software-Based Encoding and Decoding of BCH Codes,” IEEE Transactions on Computers, vol. 58, pp. 878-889, Jul 2009.
[20] X. M. Zhang and Z. F. Wang, “A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network,” IEEE Transactions on Circuits and Systems Ii-Express Briefs, vol. 59, pp. 663-667, Oct 2012.
[21] J. H. Baek and M. H. Sunwoo, “New degree computationless modified Euclid algorithm and architecture for Reed-Solomon decoder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 915-920, Aug 2006.
[22] S. Lee, H. Lee, J. Shin, and J. S. Ko, “A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders,” IEEE International Symposium on Circuits and Systems, pp. 901-904, 2007.
[23] J. Baek and M. H. Sunwoo, “New Cost-Effective Simplified Euclid’s Algorithm for Reed-Solomon Decoders,” Journal of Signal Processing Systems for Signal Image and Video Technology, vol. 71, pp. 159-168, May 2013.
[24] R. G. Gallager, “Low-Density Parity-Check Codes,” IRE Transactions on Information Theory, vol. 8, pp. 21–28, 1962.
[25] C. Y. Lin, C. C. Wei, and M. K. Ku, “Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E94a, pp. 773-780, Feb 2011.
[26] K. Zhang, X. M. Huang, and Z. F. Wang, “A High-Throughput LDPC Decoder Architecture With Rate Compatibility,” IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, pp. 839-847, Apr 2011.
[27] J. F. Canny, “A computational approach to edge detection,” IEEE Trans Pattern Analysis and Machine Intelligence, vol. 8, pp. 679-698, 1986.
[28] P. Soille, Morphological Image Analysis-Principles and Applications: Springer, 2003.
[29] H. P. Kramer and J. B. Bruckner, “Iterations of a non-linear transformation for enhancement of digital images,” Pattern Recognition, vol. 7, pp. 53–58, 1975.
[30] T. Y. Zhang and C. Y. Suen, “A fast parallel algorithm for thinning digital pattern,” Communications of the ACM, vol. 27, pp. 236-239, 1984.
[31] K. Zhang, X. M. Huang, and Z. F. Wang, “High-Throughput Layered Decoder Implementation for Quasi-Cyclic LDPC Codes,” IEEE Journal on Selected Areas in Communications, vol. 27, pp. 985-994, Aug 2009.
[32] C. H. Chen, C. M. Kuo, C. Y. Chen, and J. H. Dai, “The design and synthesis using hierarchical robotic discrete-event modeling,” Journal of Vibration and Control, 2012.
[33] S. Kopparthi and D. M. Gruenbacher, “Implementation of a Flexible Encoder for Structured Low-Density Parity-Check Codes,” IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 438 - 441, 2007.
[34] J. K. Kim, H. Yoo, and M. H. Lee, “Efficient Encoding Architecture for IEEE 802.16e LDPC Codes,” Ieice Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E91a, pp. 3607-3611, Dec 2008.
[35] T. Brack, M. Alles, F. Kienle, and N. Wehn, “A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding,” 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications, pp. 1-5, 2006.
[36] C. H. Liu, S. W. Yen, C. L. Chen, H. C. Chang, C. Y. Lee, Y. S. Hsu, and S. J. Jou, “An LDPC decoder chip based on self-routing network for IEEE 802.16e applications,” Ieee Journal of Solid-State Circuits, vol. 43, pp. 684-694, Mar 2008.

指導教授

陳慶瀚(Ching-Han Chen)

審核日期

2013-7-17

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