用於三維積體電路矽穿孔之內建測試與量測技術

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巫函諭(Han-yu Wu) 查詢紙本館藏

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論文名稱

用於三維積體電路矽穿孔之內建測試與量測技術
(Built-In Test and Measurement Techniques for Through-Silicon Vias of 3D ICs)

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摘要(中)

使用穿矽穿孔 (TSV) 的三維整合技術是目前新興的電路設計技術。三維積
體電路利用矽穿孔將多層裸晶進行堆疊，就一般製造三維積體電路而言可以分為
兩個步驟：矽穿孔的成形與製造以及裸晶的堆疊。無論是在矽穿孔的製造或是堆
疊過程中都會產生新的錯誤機制，如何有效測診斷與修復提高矽穿孔與整體三維
積體電路良率是非常重要的。
本論文中第一部分針對電源與訊號矽穿孔提出一測試與診斷技術，可以有效
將矽穿孔中的電阻性開路與短路進行判別。提出的方法中針對電阻性開路可以達
到100 歐姆而短路部分可以達到40K 歐姆的精準度。本篇論文第二部分，我們
提出了一個矽穿孔內建延遲時間量測電路(BIDM)去量測矽穿孔本身造成的傳遞
延遲時間。這部份我們同時實作了晶片去驗證我們提出的內建自我量測電路功能。
經由量測結果可以觀察出BIDM 提供了18ps 的精準度，並且相較傳統游標尺量
測電路我們提出的改良電路可以減少18%的面積成本。最後在本篇論文中我們將
利用前面所提出的測試與量測方法進行兩種應用。利用矽穿孔測試方法提升整體
電源矽穿孔良率，以及BIDM 的量測結果搭配可程式化緩衝器達到低功耗設計。
由實驗結果可以發現當冗餘電源矽穿孔可以有效提升整體電源網絡的良率。另外
在功耗分析中可以發現訊號矽穿孔的功耗藉由調整適當緩衝器驅動能力可以有
效降低功率消耗並保持一定的時間限制。

摘要(英)

Three-dimensional (3D) integration technology using through-silicon via (TSV) is one emerging integrated circuit (IC) technology. A 3D IC consists of multiple dies vertically connected by TSVs. The manufacturing process of a 3D IC can be roughly divided into two phases: die manufacturing including TSV forming and die stacking. Either the TSV forming or the die stacking may induce new failure mechanisms in the TSVs. Effective test, diagnosis and
repair techniques for TSVs thus are imperative for ensuring the quality and yield of the 3D ICs.
In the first part of this thesis, we propose a test and diagnosis scheme for power and signal TSVs. In addition to the testing of TSVs, the proposed diagnosis method can distinguish the resistive open faults from short faults of TSVs. It can detect open defect which resistance is larger than 100 and short defect which resistance is larger than 40K. In the second part of this thesis, we propose a built-in delay measurement (BIDM) method to measure the propagation delay through the signal TSVs. Also, the test chip is implemented to demonstrate the BIDM function. The proposed BIDM has the feature of high accuracy and low area cost. The measurement results of test chip show that the resolution of BIDM can reach 18ps. In comparison with a typical Vernier delay line, the proposed BIDM can achieve
18% area cost reduction. In the third part of this thesis, we introduce two applications of the proposed test method and BIDM for enhancing the yield power TSVs and minimizing the power consumption of signal TSVs. Simulation results show that the yield of power TSVs in the power delivery network can be improved by redundant power TSVs. Power analysis also shows that the power consumption of signal TSVs can be reduced by tuning the drivingcapability of programmable driver of TSVs when the number of the stacked dies not as many as expected, and delay time of TSVs still satisfies timing constraint.

關鍵字(中)

★ 三維積體電路
★ 矽穿孔
★ 內建自我測試
★ 延遲時間量測
★ 內建自我量測

關鍵字(英)

★ TSV
★ 3D IC
★ delay measurement
★ BIST
★ BIDM

論文目次

1 Introduction 1
1.1 3D Integration Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 TSV Technique and Bonding Techniques . . . . . . . . . . . . . . . . 1
1.1.2 3D IC Power Delivery Network Architecture . . . . . . . . . . . . . . 3
1.2 Test for 3D IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Testing of 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Defects in TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Test and Diagnosis Scheme for Open and Short Defective TSVs 8
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 3D Power Delivery Network . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Proposed BIST Scheme for TSVs . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Voltage Division Test Method . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Proposed Test and Diagnosis Circuit for TSV Defects . . . . . . . . . 16
2.3 Die Level Test and diagnosis Control . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.1 Comparison results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Built-in Delay Measurement Scheme for Signal TSVs 31
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.1 Challenges of Built-in Delay Measurement in 3D ICs . . . . . . . . . 32
3.1.2 Existing 2D and 3D Delay Measurement Schemes . . . . . . . . . . . 32
3.2 Proposed Built-in Delay Measurement (BIDM) Method . . . . . . . . . . . . 34
3.2.1 Architecture of the BIDM Circuit . . . . . . . . . . . . . . . . . . . . 34
3.2.2 Proposed Delay Measurement Element . . . . . . . . . . . . . . . . . 37
3.3 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.1 Performance of Measurement Result . . . . . . . . . . . . . . . . . . 42
3.3.2 Process Variation Analysis and Resolution Analysis . . . . . . . . . . 45
3.3.3 Area Overhead Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4 Test Time Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4 Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4 Power Reduction Scheme with Configurable Driver and Built-In Self Repair
Scheme for Power TSVs 58
4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1.1 Power Reduction with Configurable Driver . . . . . . . . . . . . . . . 58
4.1.2 Array Power TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Power Reduction Scheme with Configurable Driver . . . . . . . . . . . . . . 60
4.2.1 Power Reduction Scheme Architecture . . . . . . . . . . . . . . . . . 60
4.2.2 Proposed Calibration Flow in Calibration Circuit . . . . . . . . . . . 62
4.3 Built-In Self-Repair Scheme for Power TSVs . . . . . . . . . . . . . . . . . . 65
4.3.1 Test and Diagnosis Method Enhancement . . . . . . . . . . . . . . . 65
4.3.2 Test and Diagnosis Method with Built-in Self Repair Scheme for Array
Power TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.3.3 Circuit Design for Array Power TSVs . . . . . . . . . . . . . . . . . . 69
4.3.4 Fusing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.4 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 74
4.4.1 Simulation Results and Analysis for Power Reduction Scheme . . . . 74
4.4.2 Simulation Results and Analysis for Array Power TSVs Test and Diagnosis
Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5 Conclusion and Future Work 83
Bibliography 84

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指導教授

李進福(Jin-fu Li)

審核日期

2013-7-24

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