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姓名 姚閔欽(Min-Qin Yao) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 二維直角座標改良式矩形網格應用於環繞式閘極電晶體
(An Improved 2D Rectangular Mesh for Gate-All-Around MOSFET Analysis)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 本篇論文中,在探討與開發改良式矩形網格並且應用於環繞式閘極MOSFET模擬相關特性。為了探討其元件特性,我們運用基礎半導體理論波松方程式、電子連續方程式與電洞連續方程式,建構出矩形網格進行模擬。為了改善矩形網格模擬圓弧接面所產生鋸齒狀的非理想情況,而且僅用最簡單的直角座標去解決圓弧接面的問題,我們將矩形網格重新改良成三角形網格,開發出直角座標系下的三角形網格,用三角形網格做模擬,並比較三角形網格模擬出的結果是否有所改善。 摘要(英) This thesis explores and develops an improved rectangular mesh and applies it to the 2D simulation of surrounding gate MOSFET. We use Poisson’s equation, electron continuity equation and hole continuity equation to construct a rectangular mesh for 2D numerical simulation. In order to improve the ill-fitting rectangular mesh at the circular PN junction for 2D simulation, we separate each rectangular mesh into two triangular meshes. The improved rectangular mesh will be used to simulate the 2D surrounding gate MOSFET, and the new simulation result will be compared with the result from the original rectangular mesh. 關鍵字(中) ★ 環繞式閘極
★ 矩形網格
★ 三角形網格
★ 金氧半場效電晶體關鍵字(英) ★ Gate-All-Around
★ Rectangular Mesh
★ Triangular mesh
★ MOSFET論文目次 摘要 I
Abstract II
目錄 III
圖目錄 IV
表目錄 V
第一章 簡介 1
第二章 直角座標之矩形網格 3
2-1 矩形網格之定義 3
2-2 環繞式閘極 MOSFET 5
2-3 矩形網格應用於2D環繞式閘極MOSFET 7
第三章 直角座標之三角形網格 15
3-1 三角形網格之定義 15
3-2 三角形網格應用於2D環繞式閘極MOSFET 18
第四章 矩形網格與三角形網格之比較 27
4-1 半徑與氧化層厚度對VTH之影響 27
4-2 矩形網格與三角形網格VTH之比較 33
4-3 不同網格大小之比較 34
第五章 結論 38
參考文獻 40參考文獻 [1] H. IWAI, M. R. PINTO, C. S. RAFFERRY, J. E. ORISTIAN, R. W. DUTTON, “Velocity situation effect on short‐channel MOS transistor capacitance,” IEEE Transactions on Electron Devices, vol, EDL‐6, NO.3, 1985.
[2] P. P. Wang, “Device MOSFET’s,” IEEE Transactions on Electron Devices, vol ed‐25, no.7, 1978.
[3] D. A. Neamen, Semiconductor physics and devices, 3rd ed.: McGraw-Hill Companies, 2003.
[4] T. Saito, T. Saraya, T. Inukai, H. Majimi, T. Nangumo, T. Hiramoto, "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs," IEICE Trans. on Electronics, vol. E85-C, no. 5, pp. 1073-1078, 2002.
[5] J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B.-G. Park, "Design Optimization of Gate-All-Around (GAA) MOSFETs," IEEE Trans. on Nanotechnology, vol. 5, no. 3, pp. 186-191, 2006.
[6] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-Performance Fully Depleted Silicon Nanowire (Diameter ≤5 nm) Gate-All-Around CMOS Devices," IEEE Electron Device Letters, vol. 27, no. 5, pp. 383-386, 2006.
[7] D. K.Cheng, Field and wave electromagnetics, 2nd ed.: Addison-Wesley Publishing Company , Inc., 1989.
[8] A. Burenkov, J. Lorenz, "Corner Effect in Double and Triple Gate FinFETs," European Solid-State Device Research, pp. 135-138, 2003.
[9] S. M. Sze, Physics of Semiconductor Devices: John Wiley & Sons Inc., 2006.指導教授 蔡曜聰(Yao-Tsung Tsai) 審核日期 2013-7-3 推文 plurk
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