鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：53

、訪客IP：3.14.143.149

姓名

曾柏皓(Po-Hao Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製
(Ge QD SONOS nonvolatile Floating-dot transistors)

相關論文

★ 高效能矽鍺互補型電晶體之研製	★ 高速低功率P型矽鍺金氧半電晶體之研究
★ 應變型矽鍺通道金氧半電晶體之研製	★ 金屬矽化物薄膜與矽/矽鍺界面反應之研究
★ 矽鍺異質源/汲極結構與pn二極體之研製	★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製
★ 應用於單電子電晶體之矽/鍺量子點研製	★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製
★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製	★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用
★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性	★ 自對準矽奈米線金氧半場效電晶體之研製
★ 鍺浮點記憶體之研製	★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析
★ 具有自我對準電極鍺量子點單電洞電晶體之製作與物理特性研究	★ 具有自我對準下閘電極鍺量子點單電洞電晶體之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文主要是將不同鍺莫爾濃度之多晶矽鍺沉積至氮化矽層上，再利用選擇性平面氧化多晶矽鍺的方法形成不同尺寸大小的鍺量子點，並控制氧化條件將鍺量子點嵌入至氮化矽層內，形成SONOS 記憶體與鍺量子點結合的混合式 (hybrid) 記憶體元件。藉由此混合式記憶體元件，我們預期將可增進傳統SONOS 記憶體之寫入與抹除效率、記憶體窗口以及資料保存能力等記憶體特性。此外，利用氮化矽材料分離的缺陷及浮點儲存層的特性，也可以抑制傳統浮閘記憶體的側向漏電流問題，進而降低穿隧介電層的厚度，增進元件的寫入與抹除速度以及元件耐用性。再者，此元件結構及製程不僅簡單，更與現在CMOS 的製程完全相容。

摘要(英)

In this thesis, we have fabricated hybrid memory cells incorporating Ge quantum dots(QDs) into silicon/oxide/ nitride/oxide/silicon (SONOS) for nonvolatile memory application.Ge QDs are generated by thermally oxidizing poly-Si1-xGex, and their size is tunable by Ge content in poly-Si1-xGex and thermal oxidation condition.
We expected the Ge QD SONOS hybrid memory cells provide better program /erase speed, memory window, and data retention than conventional SONOS. This is benefical from the fact that both Si3N4 and QDs are discrete trapping centers, suppressing the leakage concern in floating gate memory. Therefore, the tunneling oxide thickness and the read/write bias, respectively, can be scaled down to improve program/erase speed and endurance. The most importance of this work is that the process of Ge QD SONOS hybrid memory is not only simple, but also compatible to the prevailing CMOS technology.

關鍵字(中)

★ 記憶體

關鍵字(英)

★ memory

論文目次

目錄
中文摘要............................................ i
英文摘要............................................ ii
致謝.................................................iii
目錄.................................................iV
圖目錄...............................................V
表目錄...............................................Vi
第一章簡介與研究動機
1-1 前言........................................1
1-2 非揮發性記憶體演進及介紹....................2
1-2-1 浮閘記憶體元件...............................3
1-2-2 SONOS記憶體元件..............................5
1-2-3 浮點記憶體元件...............................6
1-3 研究動機....................................9
1-4 論文架構....................................10
第二章快閃記憶體操作原理及可靠度特性
2-1 前言...........................................16
2-2 浮點記憶體操作原理...........................16
2-3 載子穿隧機制.................................17
2-3-1 Direct tunneling 穿隧機制................17
2-3-2 Fowler-Nordheim穿隧機制..................18
2-3-3 Frekel-Poole 傳輸機制....................19
2-3-4 Hot carrier injection....................20
2-3 非揮發性記憶體基本可靠度特性..................21
2-3-1 資料保存能力............................22
2-3-2 元件耐用性..............................22
第三章元件製程開發及電晶體製作流程
3-1 鍺量子點的形成...............................28
3-2 鍺量子點於氮化矽中的特性開...................29
3-2-2 鍺量子點嵌入氮化矽實驗..................29
3-3 Ge QD SONOS電晶體製作流程....................32
3-3-1 閘堆疊層製作............................33
3-3-2 閘堆疊蝕刻方法與流程....................34
3-3-3 元件後段製程流程........................37
第四章元件量測與分析
4-1 前言..........................................56
4-2 電晶體特性量測................................56
4-3 記憶體特性量測分析............................58
4-3-1 載子儲存特性分析........................58
4-3-2 寫入速度與記憶體窗口....................59
4-3-3 抹除速度................................61
4-3-4 資料保存時間............................62
4-3-5 元件耐用性..............................64
4-4 結論.........................................67
第五章總結與未來展望................................85
參考文獻

參考文獻

參考文獻
[1] Sze, Physics of Semiconductor Devices, 3nd edition,
Section 6.7
[2] 羅廣禮, "National nano device laboratories , nano
communication,” 2008.03, 15卷
[3] D. Kahng and S. M. Sze, J. of Bell syst. Tech., vol.
46, p.1288, 1967.
[4] C. Y. Lu, T. C. Lu, R. Liu, Non-volatile memory
technology-today and tomorrow, Proc. of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, July 2006,p.18.
[5] R. Degraeve, F. Schuler, B. Kaczer, M. Lorenzini, D.
Wellekens, P. Hendrickx, M. van Duuren, G. J. M.Dormans, J. Van Houdt, L. Haspeslagh, G. Groeseneken,and G.Tempel, "Analytical percolation model for predicting anomalous charge loss in flash memories", IEEE Trans. Electron Dev. 51, No.9, pp. 1392-1400,2004.
[6] M. L. French, C.-Y. Chen, H. Sathianathan, and M. H.
White, “Design and scaling of a SONOS multi-dielectric device for nonvolatile memory applications,”IEEE Trans. Comp., Packag., Manufact.Technol. A, vol. 17, pp. 390–397, Mar. 1994.
[7] Chien-Sheng Hsieh et al.,” NVM Characteristics of
Single-MOSFET Cells Using Nitride Spacers With Gate-to-
Drain NOI”, IEEE Transactionn On Electron Devices, VOL. 51, NO. 11, NOVEMBER 2004.
[8] Jeong Hee Han et al., “Fully compatible novel SNONOS
structure for improved electrical performance in NAND
Flash memories,” Solid-State Electronics 49 (2005) 1857–1861.
[9] Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F.Crabbe, and K. Chan,“A silicon nanocrystals based memory,”Appl. Phys. Lett. Vol. 68, pp.1377-1379, Mar. 1996.
[10]Sangmoo Choi et al. ,“High Density Silicon Nanocrystal Embedded in SiN Prepared by Low Energy (<500eV) SiH4 Plasma Immersion Ion Implantation for Non-volatile Memory Applications,” Tech Dig of IEDM,05, Washington; 2005.
[11]J. De Blauwe et al.,“A novel, aerosol-nanocrystal
floating-gate device for non-volatile memory applications,”IEDM Technical Digest. San Francisco, CA, 10-13 December 2000.
[12]G. Nicotra, R. A. Puglisi, S. Lombardo, and C. Spinella,“Nucleation kinetics of Si quantum dots on SiO2,”J. Appl. Phys, vol. 95, p. 2049, 2004.
[13]Tsung-Yu Chiang, Tien-Sheng Chao, Yi-Hong Wu, and Wen-LuYang,“High-Program /Erase-Speed SONOS With In Situ Silicon Nanocrystals,” IEEE Electro Device Letters, VOL. 29, NO. 10, OCTOBER 2008.
[14]Yoshihito Maeda, Nobuo Tsukamoto, Yoshiaki Yazawa, Yoshihiko Kanemitsu, and Yasuaki Masumoto, “Visible photoluminescence of Ge microcrystals embedded in SiO2 glassy matrices,” Appl. Phys. Lett. 59,
3168 (1991).
[15]Yi Shi, Kenichi Saito, Hiroki Ishikuro, and Toshiro Hiramoto, “Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals,” Journal of Applied Physics, VOL 84, NO. 4 , AUGUST 1998.
[16]Pei-Wen Li, Dept E.E. NCU ,Sub-micron Device Physics and Technology , page 192.
[17]Kaushik Roy, Hamid Mahmoodi-Meimand , “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of The IEEE, VOL. 91, NO. 2, FEBRUARY 2003.
[18]Pei-Wen Li, Dept E.E. NCU ,Sub-micron Device Physics and Technology, Thin Gate Dielectrics ,page 12
[19]Sze, Physics of Semiconductor Devices, 3nd edition, Section 8.3.2
[20]M. Lenzlinger and E. H. Snowi, “Fowler‐Nordheim Tunneling into Thermally Grown SiO2,” J. Appl. Phys. 40, 278 (1969)
[21]Sze, Physics of Semiconductor Devices, 3nd edition, Section 6.7.2
[22]Sze, Physics of Semiconductor Devices, 3nd edition, Section 4.3.4
[23]Sze, Physics of Semiconductor Devices, 3nd edition, Section 6.7.1
[24]William D.Brown and Joe E. Brewer,Nonvolatile Semiconductor Memory Technology, Section 3.5
[25]R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti,” Introduction to flash memory”, Proceedings of The IEEE, Vol. 91, pp. 489-502, 2003.
[26]P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin,” Failure mechanisms of flash cell in program/erase cycling”, Technical Digest-International Electron Devices Meeting, pp. 291-294, 1994.
[27]F. Driussi, S. Marcuzzi, P. Palestri and L. Selmi, “Gate Current in Stacked Dielectrics for Advanced FLASH
EEPROM cells,” Proceedings of ESSDERC, Grenoble, France, 2005
[28]Ying Qian Wang et al., “Electrical Characteristics of Memory Devices With a High-k HfO2 Trapping Layer
and Dual SiO2/Si3N4 Tunneling Layer,” IEEE Transactionn On Electron Devices, VOL. 54, NO. 10, OCTOBER 2007.
[29]T. Oku, T. Nakayama, M. Kuno, Y. Nozue, L. R.Wallenberg, K. Niihara and K.Suganuma, Mater. Sci. Eng. B 74, 242 (2000).
[30]M. Zacharias and P. M. Fauchet,” Blue luminescence in films containing Ge and GeO2 nanocrystals: The role of defects,” Appl. Phys. Lett., 71, 38 (1997)
[31]J-Y Zhang, Y-H Ye, X-L Tan and X-M Bao, J. Appl. Phys., 86, 6139 (1999).
[32]L. E. Jensen, M. T. Bjork, S. Jeppesen, A. I. Persson, B. J. Ohlsson, and L. Samuelson, Nano Lett.,
4, 1961 (2004).
[33]S. Vaddiraju, A. Mohite, A. Chin, M. Meyyappan, G. Sunabasekera, B. W. Alphenaar, and M. K. Sunkara, Nano. Lett.,5, 1625 (2005).
[34]賴威廷,“利用選擇性氧化單晶矽鍺形成鍺量子點之物理及電性分析,” 碩士論文,中央大學,民國九十四年
[35]張兆輝,“利用多邊形結構控制鍺量子點之位置與數量以及相關共振二極體之研究,”碩士論文,中央大學,民國九十七年
[36]C. Y. Chien, Y. R. Chang, R. N. Chang, M. S. Lee, and P. W. Li, “Formation of 3D Ge Quantum Dots Array for Advanced Photovolatics in Layer-cake Technique,” 2010 NANOKOREA symposium
[37]Kuan-Hung Chen, Chung-Yen Chien and Pei-Wen Li*, “Precise Ge quantum dot placement for quantum tunneling device,” 2010 Nanotechnology 21 055302 No. 8, August 1994 _9 The Electrochemical Society, Inc.
[38]Pei-Wen Li, Dept E.E. NCU ,Sub-micron Device Physics and Technology, Thin Gate Dielectrics , page 35
[39]Tsu-Jae King and Krishna C. Saraswat*, “Deposition and Properties of Low-Pressure Chemical-Vapor Deposited Polycrystalline Silicon-Germanium Films,” J. Electrochem. Soc., Vol. 141, No. 8, August 1994 The Electrochemical Society, Inc.
[40]李建成, “矽離子注入ONO 記憶體之可靠度與持久度研究,” 碩士論文,中原大學,民國九十二年七月
[41]吳榮軒,“鍺浮點記憶體之研製,” 碩士論文,中央大學,民國九十五年
[42]Jia-Lin Wu et al.,” Retention Reliability Improvement of SONOS Non-volatile Memory with N2O Oxidation Tunnel Oxide”, IEEE,,2006.
[43]T Sheng-Chih Lai et al., “MA BE-SONOS: A Bandgap Engineered SONOS using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation,” Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE.
[44]Min-Ta Wu et al., “Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS),” IEEE Transactionn On Electron Devices, VOL. 54, NO. 4, APRIL 2007.
[45]周明宏, “臨場沉積法成長矽奈米晶體在SONOS記憶體元件之研究,” 碩士論文,逢甲大學,民國九十五.

指導教授

李佩雯(Pei-Wen Li)

審核日期

2010-7-14

推文