應用於低電壓操作之12.5億赫茲全數位式鎖相迴路

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姓名

胡長倩(Chang-chien Hu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於低電壓操作之12.5億赫茲全數位式鎖相迴路
(An 1.25-GHz All Digital Phase-Locked Loop for Low Supply Voltage Applications)

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摘要(中)

本論文提出一個操作在1.25 GHz、擁有8個相位輸出並應用在低電壓操作的全數位式鎖相迴路。在此鎖相迴路中，使用多重相位數位控制振盪器因此可於低電壓時操作仍可獲高頻率輸出。此多重相位數位控制振盪器內含有多級次迴圈與環形延遲串列，可提升振盪頻率。於整體電路架構中，多重相位時間數位轉換器使用振盪器的多相位輸出對欲轉換之時間差值作取樣，此方法可大幅減少面積消耗。另外，在時間數位轉換器中使用時間放大器的技巧，增加轉換之時間解析度，進而減少量化雜訊的產生。
本論文之全數位式鎖相迴路使用TSMC 90 nm 1P9M CMOS製程實現晶片，其操作頻率範圍可從950 MHz到1.6 GHz，並且擁有8個相位的輸出。電路在操作電壓為0.6 V及操作頻率為1.25 GHz時，功率消耗為9.05 mW，而輸出訊號之最大峰對峰值時間抖動量為29.86 ps (3.73 %)，方均根抖動量為3.96 ps。整體晶片面積為456 × 456 um2，核心電路的面積為180 × 200 um2。

摘要(英)

This thesis presents an 1.25-GHz 8-phase all digital phase-locked loop (ADPLL) for low supply voltage applications. The ADPLL uses multistage sub-feedback loop and ring-based delay line (RB-DL) in the proposed multiphase digital controlled oscillator (MP-DCO) to obtain the higher operating frequency. A multiphase time-to-digital converter (MP-TDC) adopts the MP-DCO phase outputs to sample the timing difference. Therefore, the area of the TDC can be salved by this method. To reduce the quantization noise, a time amplifier (TA) can enhance the timing resolution of the TDC.
The experimental chip of the proposed ADPLL was implemented by TSMC 90 nm 1P9M CMOS process. The measurement results show that the output frequency range is from 950 MHz to 1.6 GHz at 0.6 V supply voltage. The peak-to-peak jitter and RMS jitter of ADPLL are 29.86 ps and 3.96 ps at 1.25-GHz frequency, respectively. The power consumption is 9.05 mW at 1.25-GHz frequency and the chip area is 456 × 456 um2.

關鍵字(中)

★ 時間數位轉換器
★ 全數位式鎖相迴路
★ 數位控制振盪器
★ 多相位振盪器

關鍵字(英)

★ ADPLL
★ Multiphase DCO
★ TDC
★ DCO

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章緒論 1
1.1 研究動機 1
1.2 研究目的及其應用 2
1.3 論文架構 4
第二章全數位式鎖相迴路先前技術探討 5
2.1 鎖相迴路種類簡介 5
2.2 全數位式鎖相迴路架構探討 6
2.2.1 低時脈抖動之全數位式鎖相迴路[2] 6
2.2.2 可抵抗PVT變異之全數位式鎖相迴路[3] 8
2.2.3 低雜訊及寬迴路頻寬之數位式鎖相迴路[4] 9
2.2.4 免校正之數位式鎖相迴路[5] 11
2.2.5 寬電壓範圍及寬操作頻率之全數位式鎖相迴路[6] 12
2.2.6 各種鎖相迴路架構規格比較 13
2.3 本論文預計規格 15
第三章多重相位數位控制振盪器並應用於時間數位轉換器 17
3.1 設計概念 17
3.2 多重相位數位控制振盪器 (MP-DCO) 18
3.2.1 多重相位數位控制振盪器公式探討[7] 18
3.2.2 多重相位數位控制振盪器架構 21
3.2.3 多重相位數位控制振盪器內部電路 22
3.2.4 多重相位數位控制振盪器模擬結果 25
3.3 多重相位時間數位轉換器(MP-TDC) 27
3.3.1 多重相位時間數位轉換器架構 27
3.3.2 多重相位時間數位轉換器內部電路 29
3.3.3 多重相位時間數位轉換器模擬結果 33
3.3.4 多重相位時間數位轉換器之位元數探討 38
第四章應用於低電壓操作之12.5億赫茲全數位式鎖相迴路 41
4.1 電路架構與操作 41
4.2 鎖相迴路系統分析[9] 42
4.2.1 全數位式鎖相迴路之S-domain分析 42
4.2.2 電荷幫浦鎖相迴路之S-domain分析 44
4.2.3 計算數位迴路濾波器之參數 45
4.3 全數位式鎖相迴路之子電路設計 47
4.3.1 相位頻率偵測器 47
4.3.2 數位迴路濾波器 48
第五章電路模擬與晶片量測結果 51
5.1 設計流程 51
5.2 佈局前電路模擬 51
5.3 電路佈局與佈局後電路模擬 53
5.4 晶片照相與量測環境設定 56
5.5 量測結果 59
5.6 規格比較 64
第六章結論與未來研究方向 67
6.1 結論 67
6.2 未來研究方向 67
參考文獻 69

參考文獻

[1] T. Sakurai, “Low Power Digital Circuit Design,” IEEE European Solid-State Circuits Conference, pp. 11-18, Sep. 2004.
[2] S.-Y. Lin, and S.-I. Liu, “A 1.5 GHz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111-3119, Nov. 2009.
[3] W. Liu, W. Li, P. Ren, C. Lin, S. Zhang, and Y. Wang, “A PVT tolerant 10 to 500 MHz all-digital phase-locked loop with coupled TDC and DCO,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 314-321, Feb. 2010.
[4] M. Lee, M. E. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808-2816, Oct. 2009.
[5] S.-W. Chen, D. Su, and S. Mehta, ‘‘A calibration-free 800 MHz fractional-N digital PLL with embedded TDC,’’ in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 472-473.
[6] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, ‘‘A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,’’ IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008.
[7] H.-Y. Huang, and F.-C. Tsai, ‘‘Analysis and optimization of ring oscillator using sub-feedback scheme,’’ in Proc. IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems, Apr. 2009, pp. 28-29.
[8] M. Lee, and A. A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr. 2008.
[9] V. Kratyuk, ‘‘Digital phase-locked loops for multi-GHz clock generation,” OSU Ph. D. Thesis, Dec. 2006.
[10] W. Grollitsch, R. Nonis, and N. D. Dalt, ‘‘A 1.4 psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS,’’ in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 478-479.
[11] A. V. Rylyakov, J. A. Tierno, D. Z. Turker, and J.-O. Plouchart, ‘‘A modular all-digital PLL architecture enabling both 1-to-2 GHz and 24-to-32 GHz operation in 65 nm CMOS,’’ in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 516-517.
[12] K.-F. Un, P.-I. Mak, and R. P. Martins, ‘‘Analysis and design of open-loop multiphase local-oscillator generator for wireless applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 57, no. 5, pp. 970-981, May 2010.
[13] C.-C. Chung, and C.-Y. Lee, ‘‘An all-digital phase-locked loop for high-speed clock generation,’’ IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003.
[14] B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, ‘‘A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,’’ IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855-863, Apr. 2008.
[15] M. Z. Straayer, and M. H. Perrott, ‘‘A multi-path gated ring oscillator TDC with first-order noise shaping,’’ IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, Apr. 2009.
[16] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, ‘‘A portable digitally controlled oscillator using novel varactors,’’ IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 52, no. 5, pp. 233-237, May 2005.
[17] M.-N. Mohammad, and S. Manoj, ‘‘A monotonic digitally controlled delay element,’’ IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2212-2219, Nov. 2005.
[18] B.-M. Moon, Y.-J. Park, and D.-K. Jeong, ‘‘Monotonic wide-range digitally controlled oscillator compensated for supply voltage variatio,’’ IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 55, no. 10, pp. 1036-1040, Oct. 2008.
[19] D. Sheng, C.-C. Chung, and C.-Y. Lee, ‘‘An ultra-low-power and portable digitally controlled oscillator for SoC applications,’’ IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 54, no. 11, pp. 954-958, Nov. 2007.
[20] A. Alvandpour, R. K. Krishnamurthy, D. Eckerbert, S. Apperson, B. Bloechel, and S. Borkar, ‘‘A 3.5 GHz 32 mW 150 nm multiphase clock generator for high-performance microprocessors,’’ in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 112-113.
[21] S.-I. Liu, and C.-Y. Yang, ‘‘Phase-locked loop,’’ Taipei: Tsang Hai Book Publishing Co., Nov. 2006.
[22] Y.-T. Chen, ‘‘An ultra low power all digital PLL for wide power supply range,” NCU M. Thesis, Oct. 2009.
[23] Y.-L. Chang, ‘‘A digital PLL using current-step controller for wide operating range application,” NCU M. Thesis, Jan. 2010.
[24] J.-S. Huang, ‘‘A 0.5-V 1.25-GHz phase-locked loop,” NCU M. Thesis, Dec. 2008.
[25] C.-C. Wu, ‘‘A low power design of fast locking all digital phase locked loop,” NCCU M. Thesis, Jul. 2008.

指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2010-10-19

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