電遷移誘發錫/銅界面(錫,銅)原子通量之交互關係及其對錫/銅銲點電遷移失效機制影響研究

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：56

、訪客IP：3.144.235.141

姓名

曾華偉(Hua-wei Tseng) 查詢紙本館藏

畢業系所

化學工程與材料工程學系

論文名稱

電遷移誘發錫/銅界面(錫,銅)原子通量之交互關係及其對錫/銅銲點電遷移失效機制影響研究
(Study of interaction between electromigration-induced (Sn,Cu) atomic fluxes at Sn/Cu interface and the effect on EM-induced failure modes at Sn/Cu joint interface)

相關論文

★ Au濃度Cu濃度體積效應於Sn-Ag-Cu無鉛銲料與Au/Ni表面處理層反應綜合影響之研究	★ 薄型化氮化鎵發光二極體在銅填孔載具的研究
★ 248 nm準分子雷射對鋁薄膜的臨界破壞性質研究	★ 無光罩藍寶石基材蝕刻及其在發光二極體之運用研究
★ N-GaN表面之六角錐成長機制及其光學特性分析	★ 藍寶石基板表面和內部原子排列影響Pt薄鍍膜之de-wetting行為
★ 藍寶石基板表面原子對蝕刻液分子的屏蔽效應影響圖案生成行為及其應用	★ 陽離子、陰離子與陰陽離子共摻雜對於p型氧化錫薄膜之電性之影響研究與陽離子空缺誘導模型建立
★ 通過水熱和溶劑熱法合成銅奈米晶體之研究	★ 自生反應阻障層 Cu-Ni-Sn 化合物在覆晶式封裝之研究
★ 含銅鎳之錫薄膜線之電致遷移研究	★ 微量銅添加於錫銲點對電遷移效應的影響及鎳金屬墊層在電遷移效應下消耗行為的研究
★ 電遷移誘發銅墊層消耗動力學之研究	★ 不同無鉛銲料銦錫'錫銀銅合金與塊材鎳及薄膜鎳之濕潤研究
★ 錫鎳覆晶接點之電遷移研究	★ 錫表面處理層之銅含量對錫鬚生長及介面反應之影響

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

現今微電子構裝系統中，為容納更高密度的I/O（Input/Output）數目在高階IC晶片上，覆晶接點(flip-chip bumps)尺寸將大幅縮小至50 μm以下。如此，每個覆晶接點所承受的電流密度將會高達104 A/cm2或更高，進而造成電遷移效應誘發失效行為(electromigration-induced failure)，此失效行為將嚴重IC晶片內覆晶接點之可靠度。因此，在此博士論文中，於第三章，我們先利用一個基本的覆晶式銅/錫/銅銲點結構去探討會發生的電遷移誘發失效模式與原因。在第四章中，深入去探討陰極銅/錫銲點界面其電遷移誘發失效行為機制；我們計算出銅金屬墊層其在電遷移效應下的消耗活化能(QEM)和銅在錫母體中的有效碰撞係數(effective charge number, Z*Cu/Sn)；得到這些參數後，我們可以定量出電遷移誘發銅在錫的電遷移原子通量(JCu,EM)和銅原子溶解通量(JCu,diss.)。一旦，得到以上兩個電遷移誘發原子通量，可以建立一個動力學模型去定義出：(1)電遷移誘發銅原子溶解通量主要驅動力和(2)抑制錫在錫母體中電遷移原子通量的“合金效應”。將JCu,EM和JCu,diss.做相等可以取得固定電流密度下的臨界溫度值(Tcrit.)，再利用這些臨界溫度值去描繪出陰極銅/錫界面電遷移誘發失效圖。同時也發現陰極界面上錫銅化合物的成長和電流密度與測試溫度有極大的關係。最後在第五章，根據先前學者的基礎模型，我們建構出更可靠與正確的陰極界面電遷移失效行為圖(銅墊層消耗，錫孔洞形成，陰極界面錫銅化合物成長)。

摘要(英)

Abstract
Due to the number of the I/O (input/outout) counts in the advanced IC will continue to increase quickly; the diameter of flip-chip bumps will approach to 50 μm and below. The current density in each flip-chip bumps could reach 104 Amp/cm2 or higher. While the high density of current flowing through the flip-chip solder bumps, EM (electromigration)-induced failure has become a serious reliability issues for the solder joint. Hence, in this work, we will first discuss what kinds of EM-induced failures would occur in a flip-chip Cu/Sn/Cu solder joint under EM test in Chapter 3. In Chapter 4, the entire EM-induced failure modes at the cathode Cu/Sn solder joint interface would be discussed in a great detail. In Chapter 4, we also calculated the activation energy for the Cu-pad consumption under the EM effect (QEM), and the effective charge number (Z* value of Cu in Sn (Z*Cu/Sn)). By knowing the activation energy for the Cu-pad consumption and the effective charge number, we can quantify both Cu EM flux in Sn solder matrix (JCu,EM) and EM-induced Cu pad dissolution flux (JCu,diss.). Once the above two EM-induced fluxes are deduced, a kinetic model is build to define: (1) the main driving force of the EM-induced Cu-pad dissolution and (2) “alloy effect” retarding the Sn EM flux in the Sn solder matrix. By equaling the JCu,EM and the JCu,diss., we can obtain the a critical temperature (Tcrit.) at a constant current density. Then, we can use various critical temperatures to plot a EM-induced failure map at the cathode Cu/Sn interface under EM effect. Also, the growth of interfacial Cu-Sn compounds at the cathode interface has been found to have a strong relationship with current densities and EM-test temperatures. Finally, based on previous researcher’s model, we can construct a more reliable and accurate plot of the EM failure behavior at the cathode Cu/Sn interface (Cu-pad consumption, Sn-voids formation, cathode IMCs formation) under EM effect in Chapter 5.

關鍵字(中)

★ 覆晶封裝技術
★ 電遷移效應

關鍵字(英)

★ electromigration effect
★ flip-chip technology

論文目次

Table of contents
Abstract (Chinese)...I I
Abstract (English)...II
Table of contents...III
List of figures...VI
List of tables...X
Chapter 1 Introduction...1
1.1 Flip-chip technology...1
1.1-1 Introduction of flip-chip technology...1
1.1-2 Pb-free solders...3
1.2 Basic of electromigration in solder joints...5
1.3 EM-induced failures at flip-chip cathode solder joints...6
1.3-1 EM-caused Sn-voids formation at cathode IMCs/solder interface...7
1.3-2 EM-induced dissolution of the Cu metal bond pad or the Cu trace lines...7
1.3-3 EM effect on interfacial compound formation...8
Chapter 2 Motivation...10
Chapter 3 Mechanism of EM-induced failures at Cu/Sn/Cu joint interfaces...13
3.1 EM-induced failures at Cu/Sn/Cu joint interfaces...13
3.1-1 Experimental procedures...13
3.1-2 Simulation of the electrical current density distribution...14
3.1-3 EM-induced failures at cathode Cu/Sn joint interface...15
3.1-4 Evolution of Cu atomic fluxes induced by EM effect in the flip-chip Cu/Sn/Cu solder joint...17
3.2 Mechanism of EM-induced failures at the flip-chip Cu/Sn/Cu solder joint...21
3.3 Summary...28
Chapter 4 Factors affecting the EM-induced failures in Cu/Sn/Cu solder joint...29
4.1 Activation energy of the EM-induced Cu-pad consumption...29
4.1-1 Experimental procedures...29
4.1-2 Interfacial reactions and Cu-pad consumption without current stressing...30
4.1-3 Interfacial reactions and Cu-pad consumption with current stressing...34
4.2 Verification of the driving force for EM-induced Cu dissolution by using Cu/Sn/Cu U-groove samples...40
4.2-1 Experimental procedures...41
4.2-2 Discussion of driving force of the EM-induced Cu-pad dissolution...42
4.3 Determination of effective charge number of Cu in Sn matrix...49
4.3-1 Experimental procedures...49
4.3-2 Calculation of effective charge number of Cu in Sn matrix...50
4.4 Alloy effect on the Sn EM flux...56
4.4-1 Kinetic analysis of cathode IMCs/Sn interface under current stressing...57
4.4-2 Experimental procedures...60
4.5 Summary...67
Chapter 5 Constructing EM failure behavior map at the cathode Cu/Sn interface...69
5.1 EM-induced failure map at the cathode Cu/Sn interface...69
5.1-1 References selected for constructing EM-induced failure map at the cathode Cu/Sn interface...71
5.1-2 Joule-heating effect in EM-induced failure map...74
5.2 Cathode IMCs formation under EM effect...76
5.3 EM failure behavior at the cathode Cu/Sn interface under current stressing...81
5.3-1 Cathode IMCs formation with temperatures and current densities...81
5.3-2 Constructing EM failure behavior map at the cathode Cu/Sn interface: Cu-pad consumption, Sn-voids formation, cathode IMCs formation...83
Chapter 6 Conclusion...85
Reference ...87
Appendix (A): Evolution of Ag3Sn compound formation in Ni/Sn5Ag/Cu solder joint...91
Appendix (B): Ag electromigration against electron flow in Sn5Ag/Cu solder bump...98

參考文獻

[1] A. Rahn (ed.), in The Basics of Soldering (John Wiely & Sons, New York, 1993).
[2] L.F. Miller, Proc. 31st IEEE Electron. Comp. Conf. (New York: IEEE, 1968), pp.52–56.
[3] V.C. Marcotte and N.G. Koopman, Proc. 31st IEEE Electron. Comp. Conf. (New York: IEEE, 1981), p. 157–162.
[4] S. J. Wang and C.Y. Liu, Journal of electronic materials, 32, 1303, (2003)
[5] C. E. Ho, S. C. Yang, C. R. Kao, J Mater Sci: Mater Electron, 18, 155, (2007).
[6] K. Zeng, K. N. Tu, Mater. Sci. Eng. R, 38, 55 (2002).
[7] J. Cannis, Green IC packaging, Adv. Packag., 8, 33, (2001).
[8] K. N. Tu, J. W. Mayer, L. C. Feldman, Electronic thin film science: for electrical engineers and materials scientists, (Prentice Hall, 1992), pp.355-368.
[9] D. Edenfeld, A. B. Kahng, M. Rodgers, Y. Zorian, International Technology Roadmap for Semiconductor, Semiconductor Industry Association, San Jose, CA, (2003).
[10] Y. H. Lin and C. R. Kao, J. Electron. Mater. 34, 27, (2005).
[11] S. Brandenburg and S. Yeh, Surface Mount International Conference and Exposition, SMI 98 Proceedings (1998), p. 337.
[12] W. J. Choi, E. C. C. Yeh, K. N. Tu, J. Appl. Phys., 94, 5665, (2003).
[13] Y. C. Hu, Y. H. Lin, C. R. Kao, and K. N. Tu, J. Mater. Res., 18, 2544, (2003).
[14] “Lead-Free Solder Project Final Report”, NCMS Report 0401RE96, Ann Arbor, MI, August (1997).
[15] B. P. Richards, C. L. Levoguer, C. P. Hunt, K. Nimmo, S. Peters, and P. Cusack, “An Analysis of The Current Status of Lead-Free Soldering”, British Department of Trade and Industry Report, April (1999).
[16] S. K. Kang, D. Y. Shih, D. Leonard, D. W. Henderson, T. Gosselin, S. Cho, Jin Yu, and W. K. Choi, JOM, 56, 34, (2004).
[17] H. K. Kim and K. N. Tu, Phys. Rev. B, 53, 16027, (1996).
[18] S. W. Chen, C. M. Chen, and W. C. Liu, J. Electron. Mater., 27, 1193, (1998).
[19] C. M. Chen and S. W. Chen, J. Electron. Mater., 28, 902, (1999).
[20] C. M. Chen and S. W. Chen, J. Appl. Phys., 90, 1208, (2001).
[21] S. W. Chen and C. M. Chen, JOM 55, 62 (2003).
[22] H. Gan and K. N. Tu, J. Appl. Phys. 97, 063514 (2005).
[23] C. T. Lin, Y. C. Chuang, S. J. Wang, and C. Y. Liu, Appl. Phys. Lett., 89, 101906, (2006).
[24] 莊曜群, “銅覆晶墊層銲點界面之電遷移失效模式研究”, 國立中央大學化學工程與材料工程所, 博士論文, (2008).
[25] V. I. Dybkov, Growth Kinetics of Chemical Compound Layers, (Cambridge International Science, Cambridge,1998).
[26] Brook Chao, S. H. Chae, X. Zhang, K. H. Lu, J. Im, and P. S. Ho, Acta Materialia, 55, 2805, (2007).
[27] Z. Mei, A. J. Sunwoo, J. W. Morris Jr., Metall. Trans. A, 23, 857, (1992).
[28] M. Onishi, H. Fujibuch, Trans. Jpn. Inst. Met. 19, 539, (1975).
[29] A. Gangulee and F. M. d’Heurle, Thin Solid Films, 16, 227, (1973).
[30] R. Rosenberg, J. Vac. Sci. Technol., 9, 289, (1972).
[31] J. van Ek, J. P. Dekker, and A. Lodder, Phys. Pev, B 52, 8794, (1995).
[32] C. Y. Liu, Lin Ke, Y. C. Chuang, and S. J. Wang, J. Appl. Phys., 100, 083702, (2006).
[33] C. Yu and H. Lu, J. Appl. Phys., 102, 054904, (2007).
[34] C. C. Lu, S. J. Wang, and C. Y. Liu, J. Electron. Mater., 32, 1515, (2003).
[35] D. Ma, W. D. Wang, and S. K. Lahiri, J. Appl. Phys., 91, 3312, (2002).
[36] I. Ames, F. M. d’ Heurle, and R. E. Horstmann, IBM J. Res. Develop, 44, 89, (2000).
[37] T. Y. Lee, K. N. Tu, and D. R. Frear, J. Appl. Phys., 90, 4502, (2001).
[38] Y. L. Lin, C. W. Chang, C. M. Tsai, C. W. Lee, and C. R. Kao, J. Electron. Mater., 35, 1010, (2006).
[39] K. Zeng, R. Stierman, T. C. Chiu, D. Edwards, K. Ano, and K. N. Tu, J. Appl. Phys., 97, 024508, (2005).
[40] W. M. Tang, A. Q. He, Q. Liu, D. G. Ivey, Trans. Nonferrous Met. Soc. China, 20, 90, (2010).
[41] L. Snugovsky, C. Cermignani, D. D. Perovic, and J. W. Rutter, J. Electron. Mater., 33, 1313, (2004).
[42] M. Ding, G. Wang, B. Chao, P. S. Ho, P. Su, T. Uehling, J. Appl. Phys., 99, 094906, (2006).
[43] P. S. Ho and T. Kwok, Rep. Prog. Phys., 52, 321, (1989).
[44] T. Y. Lee, K. N. Tu, and D. R. Frear, J. Appl. Phys., 90, 4502, (2001).
[45] J. D. Wu, C. W. Lee, S. Y. Wu, and S. Li, Proceedings of the 42nd Annual International Reliability Physics Symposium, Phoenix (IEEE, New York, 2004), p. 565.
[46] C. Yu and H. Lu, J. Appl. Phys., 102, 054904, (2007).
[47] H. W. Tseng, Y. T. Yeh, K. Y. Lin, and C. Y. Liu, Electrochem. Solid State Lett., 12, H445, (2009).
[48] J. H. Lee and Y. B. Park, J. Electron. Mater., 38, 2194, (2009).
[49] Y. H. Hsiao, H. W. Tseng, and C. Y. Liu, J. Electron. Mater., 38, 2573, (2009).
[50] Y. Alfred, E. Bernd, L. Charles, Microelectron. Reliab., 48, 1847, (2008).
[51] L. Xu, J. K. Han, J. J. Liang, K. N. Tu, Y. S. Lai, Appl. Phys. Lett., 92, 262104, (2008).
[52] W. H. Wu, H. L. Chung, C. N. Chen, C. E. Ho, J. Electron. Mater., 38, 2563, (2009).
[53] M. H. R. Jen, L. C. Liu, Y. S. Lai, Microelectron. Reliab., 49, 734, (2009).
[54] 廖珮嵐, “Cu-Sn-Cu覆晶結構之陰極銅箔消耗與電遷移失效模式”, 國立中央大學化學工程與材料工程所, 碩士論文, (2007).
[55] Y. C. Chan and D. Yang, Prog. Mater. Sci., 55, 428, (2010).
[56] C. Y. Liu, Chih Chen, K. N. Tu, J. Appl. Phys., 88, 5703, (2000).
[57] T. Y. Lee, K. N. Tu, S. M. Kuo and D. R. Frear, J. Appl. Phys., 89, 3189, (2001).
[58] C. E. Ho, A. Lee, K. N. Subramanian, J. Mater. Sci.: Mater. Electron., 18, 569, (2007)
[59] C. Chen and S. W. Liang, J. Mater. Sci.: Mater. Electron., 18, 259, (2007).
[60] S. W. Liang, Y. W. Chang, and C. Chen, J. Electron. Mater., 36, 1348, (2007).
[61] D. R. Frear, S. N. Burchett, H. S. Morgan, and J. H. Lau, The Mechanics of Solder Alloy Interconnects, p. 60 (Van Nostrand Reinhold, New York, 1994).

指導教授

劉正毓(Cheng-yi Liu)

審核日期

2010-12-23

推文