使用於矽穿孔耦合分析之垂直十字鏈基板結構

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姓名

游祥凱(Siang-kai You) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用於矽穿孔耦合分析之垂直十字鏈基板結構
(VCCSS: A Vertical-Cross-Chain Substrate Structure Used in TSV Coupling Analysis)

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摘要(中)

隨著三維晶片裡的矽穿孔密度增加，兩訊號互相干擾將會造成訊號的傳輸品質發生問題。TSV串音干擾主要的因素取決於TSV diameter及兩TSV之間的間距(spacing)。此外，矽基板的厚度及參雜濃度也發揮了重要的作用，它們影響基板接地的有效性。本論文主要提出等效垂直十字鏈基板結構(Vertical-Cross-Chain Substrate Structure;VCCSS) 針對兩TSV之間的耦合效應來加強模擬的精準度，此VCCSS模型是single cross cube的擴展延伸，其中矽基板是被垂直分段成好幾層。相對應的TSV model也被等效均勻切割，它們結合起來去建構等效的模型來分析耦合效應。特別是基板有接地時，從模擬結果中得到可提高18.5%的準確度，展現出從TSV到頂部基板接地會有一收集發散電流的深度效應。從串音干擾預防的觀點來看，無論是基板接地或是Ground TSV的方式皆比使用間距來的有效。

摘要(英)

As to increase the Through-Silicon-Via (TSV) density in the three-dimensional chip integration, the quality of signal transmission may be problem on the two signals interfering with each other. The major factors of TSV crosstalk are determined by the diameter of TSVs and their spacing between two TSVs. Besides, the thickness and the doping concentration of the silicon substrate also play a key role, where they determine the effectiveness of substrate-grounds. In this thesis, a Vertical-Cross-Chain Substrate Structure (VCCSS) is proposed to enhance the simulation accuracy for TSV coupling analysis. The VCCSS model is an extension of single cross cube, in which the substrate is segmented vertically into several layers. By the conjunction of the corresponding segmented T-model of TSV, they are combined to construct the electrical equivalence under coupling analysis. It is shown that VCCSS will gain the improved accuracy to 18.5%, especially for the cases of substrate grounding, which exhibit the depth effect of converging the emitted current from TSVs into top ground pad. From the viewpoint of crosstalk prevention, both the ways of substrate and TSV grounding are more effective than spacing.

關鍵字(中)

★ 矽穿孔
★ 矽基板
★ 參雜濃度
★ 耦合

關鍵字(英)

★ TSV
★ silicon substrate
★ doping concentration
★ coupling

論文目次

中文摘要I
ABSTRACTII
目錄IV
圖目錄VI
表目錄VIII
第一章簡介1
1.1前言1
1.2動機3
1.3 論文組織4
第二章串音現象5
2.1串音現象基本概念5
2.2串音雜訊之來源6
2.3串音現象之效應[15]12
第三章模型(MODEL)17
3.1介紹17
3.1.1 說明17
3.1.2 TSV不同的名詞18
3.2 TSV製程19
3.2.1 先鑽孔(Via First)[14]19
3.2.2 後鑽孔(Via Last)[14]21
3.3 矽穿孔本質結構及矽穿孔與矽基板模型22
3.3.1 矽穿孔本質結構22
3.3.2 Single TSV模型25
3.3.3 TSVs與矽基板(silicon substrate)模型28
第四章耦合效應運用在TSV LINEAR ARRAY 1×5的模擬34
4.1實驗流程34
4.2 COUPLING之NOISE分析35
4.3COUPLING NOISE模擬結果41
第五章結論47
參考文獻48

參考文獻

[1]J. Pak, C. Ryu, and J. Kim, “Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation,” International Conference on Electronic Materials and Packaging 2007, pp. 351-354, May 2008.
[2]R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L.R. Zheng, “Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits,” IEEE International Conference on 3D System Integration 2009, pp. 1-8, Sep. 2009.
[3]G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical Modeling and Characterization of Through-Silicon Vias (TSVs) for 3-D Integrated Circuits,” IEEE Transactions on Electron Devices, pp. 256-262, Jan. 2010.
[4]S.W. Tu, Y.W. Chang, and J.Y. Jou, “RLC Coupling-Aware Simulation and On-Chip BUS Encoding for Delay Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 2258-2264, Oct. 2006.
[5]J. Cho, J. Shim, E. Song, J.S. Pak, J. Lee, H. Lee, K. Park and J. Kim, “Active Circuit to Through Silicon Via (TSV) Noise Coupling,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2009, pp. 97-100, Oct. 2009.
[6]R. Gharpurey, and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits,” IEEE Journal of Solid-State Circuits, pp. 344-353, Mar. 1996.
[7]C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging,” Electronics System integration Technology Conference, pp.215-220, Sep. 2006.
[8]E. Salman, and E. G. Friedman, “Methodology for placing localized guard rings to reduce substrate noise in mixed-signal circuits,” Research in Microelectronics and Electronics 2008, pp. 85-88, Apr. 2008.
[9]J. S. Yang, and A.R. Neureuther, “Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner,” International Symposium on Quality Electronic Design 2008, pp. 352-356, Mar.2008.
[10]J. Kim, E. Song, J. Cho, J.S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Through silicon via (TSV) equalizer,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2009, pp. 13-16, Oct. 2009.
[11]T. Bandyopadhyay, R. Chatterjee, C. Daehyun, M. Swaminathan, and R. Tummala, “Electrical modeling of Through Silicon and Package Vias,” IEEE International Conference on 3D System Integration 2009, pp. 1-8, Sep. 2009.
[12]N.H. Khan, S.M. Alam, and S. Hassoun, “Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs,” IEEE International Conference on 3D System Integration 2009, pp. 1-7, Sep. 2009.
[13]唐經洲, “3D IC有其他好處嗎？,” CTimes,零組件雜誌, 五月號, 2009.
[14]由3D IC製程變化看技術發展挑戰, 九月號 2008, http://edm.itri.org.tw/enews/epaper/9709/d01.htm
[15]陳耿男, “匯流排上的時間延遲及交談失真的偵錯設計技巧,” 國立中央大學電機工程學系碩士論文 2006.
[16]鈴木茂夫著, 白中和譯, “容易瞭解的高頻技術入門,” 建興文化事業有限公司 2007.
[17]張嘉華, 唐經洲, “3D IC應用市場核心技術TSV的概況與未來,” CTimes, 零組件雜誌, 九月號2009.
[18]唐經洲, “為何不用SoC？,” CTimes,零組件雜誌,四月號2009.
[19]L. Hui Chen and M. Marek-Sadowska, “Aggressor Alignment for Worst-Case Crosstalk Noise,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 612–621, May 2001.
[20]K. J. Chang, N. H. Chang, S. Y. Oh, and K. Lee, “Parameterized SPICE Subcircuits for Multilevel Interconnect Modeling and Simulation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, pp. 779–789, Nov. 1992.

指導教授

陳繼展、梁新聰、陳竹一
(Ji-Jan Chen、Hsing-Chung Liang、Jwu-E Chen)

審核日期

2010-11-3

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