應用於具有擴展頻譜串列資料之每秒30億位元全速率資料回復電路

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姓名

劉許驊(Hsu-Hua Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於具有擴展頻譜串列資料之每秒30億位元全速率資料回復電路
(Design and Implementation of 3 Gbps Full-Rate Data Recovery Circuit for Serial Link Data Transmission with Spread-Spectrum Clocking)

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摘要(中)

隨著資料傳輸速率需求的增加，對於輸入與輸出的頻寬限制也與日俱增，因此高速串列傳輸系統逐漸取代傳統的並列傳輸方式，例如應用在乙太網路及光纖網路上的OC-192，與著重於有線或是匯流排上的應用有PCI-E、SATA…等系統，在這些規格所傳輸的速率已達到 Gbps的等級。本論文之設計主要針對串列有線傳輸系統中的SATA接收端規格為設計藍圖，採用雙迴路的方式實現，基本架構為延遲鎖定迴路，並加上頻率偏移校正迴路解決頻率偏移的問題，利用全速率取樣方式實現資料回復電路。
本論文實現應用於3 Gbps的串列傳輸系統中之資料回復電路。此系統中具有延遲鎖定迴路與頻率偏移校正迴路之雙迴路設計。延遲鎖定迴路用來做資料與時脈間的相位追鎖，但由於延遲鎖定迴路本身並無頻率追鎖的能力，所以當資料與時脈間存在頻率偏移時可能因此造成系統的不穩定，故加上頻率偏移校正迴路在資料與時脈間產生頻率偏移時，提供額外的相位補償給延遲鎖定迴路，最後延遲鎖定迴路校準時脈到達最佳取樣位置。
本論文之全速率資料回復電路使用TSMC 90 nm 1P9M CMOS製程實現晶片，其輸入資料為3 Gbps差動訊號，操作時脈為四相位3 GHz訊號。整體晶片面積為534 um ? 556 um，核心電路的面積為325 um ? 278 um。電路在操作電壓為1.2V時，功率消耗為23.8mW。

摘要(英)

As the increase of the demands for the high speed data rate, the input-output bandwidth will progress with each passing day. Therefore, the high speed serial transmission systems have replaced traditional parallel transmission systems gradually. For example, OC-192 is applied in Gigabit Ethernet and Fiber channel. PCI-E and SATA are use in wire or bus serial links. Most of the system operates at the data rate attending to the level of Gbps. For the design of the SATA receiver circuit system, the study introduces the dual-loop-based data recovery circuit architecture, and develops the circuit on the full-rate sampling data technique. The architecture consists of a delay-locked loop (DLL) and a frequency offset calibration loop. Thus, based on the calibration loop, the issue of the frequency offset can be eliminated.
The data recovery circuit architecture is implemented for the application to the 3 Gbps serial link system. The data recovery architecture is composed of DLL and the frequency offset calibration loop. Traditionally, due to the only phase tracking capability for DLL, use DLL to track the phase difference between clock and data may cause the frequency offset problem. It means that, when the frequency difference exists between the clock and data, the DLL can not lock in phase and yields the unstable system. Accordingly, the use of the frequency offset calibration loop can compensate the phase in tracking data. Finally, as the DLL adjusts the delay clock phase, the data is recovered in success.
This study implements the full-rate data recovery circuit in TSMC 90 nm 1P9M CMOS process. The input signal is the 3 Gbps differential data, and the input clock is 3 GHz with the 4 phase signal. The chip area is 534 um ? 556 um and the core area is 325 um ? 278 um. The power consumption is 30 mW at supply of 1.2V.

關鍵字(中)

★ 延遲鎖定迴路
★ 資料回復電路
★ 時脈與資料回復電路

關鍵字(英)

★ Delay-locked loop
★ Clock and data recovery
★ Data recovery

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章資料回復電路之時脈抖動分析 5
2.1 時脈抖動簡介 5
2.2 定量性抖動(Deterministic Jitter，DJ) 6
2.2.1 週期性抖動(Periodic Jitter，PJ) 6
2.2.2 責任週期失真(Duty Cycle Distortion，DCD) 7
2.2.3 符碼間干擾(Inter Symbol Interference，ISI) 8
2.3 隨機抖動(Random Jitter，RJ) 9
2.4 眼圖分析(Eye Diagram Analysis) 10
2.5 誤碼率(Bit Error Rate，BER) 11
2.6 時脈與資料回復電路的抖動參數 14
2.6.1 抖動轉移函數(Jitter Transfer Function，JTF) 14
第3章時脈與資料回復電路簡介 18
3.1 時脈與資料回復電路簡介 18
3.1.1 串列連接與並列連接 19
3.1.2 資料形式 19
3.2 取樣速率(Sample Rate) 20
3.3 傳統時脈與資料回復電路架構 21
3.3.1 鎖相迴路式時脈與資料回復電路 21
3.3.2 延遲鎖相迴路式時脈與資料回復電路 23
3.3.3 超取樣式時脈與資料回復電路 24
3.3.4 相位選擇式時脈與資料回復電路 25
第4章應用於具有擴展頻譜串列資料之全速率資料回復電路 26
4.1 電路架構與操作 26
4.2 系統分析與模擬 28
4.2.1 延遲鎖定迴路分析 29
4.2.2 延遲鎖定迴路行為模擬 32
4.2.3 頻率偏移分析 34
4.3 延遲鎖定迴路 37
4.3.1 Bang-Bang相位偵測器 38
4.3.2 充電泵電路與迴路濾波器 41
4.3.3 電壓控制延遲線電路 44
4.3.4 延遲鎖定迴路模擬 48
4.4 頻率偏移校正迴路 50
4.4.1 頻率偵測器電路 51
4.4.2 計數器電路 53
4.4.3 相位選擇器電路 54
4.4.4 頻率偏移校正迴路模擬 55
4.4.5 資料回復電路模擬 56
4.5 規格比較表 57
第5章晶片佈局與量測 58
5.1 資料回復電路佈局 58
5.1.1 晶片封裝 59
5.1.2 佈局規劃與電源規劃 60
5.1.3 PAD and Seal-Ring 61
5.2 量測考量 62
5.2.1 量測環境 62
5.2.2 通道模型 63
5.2.3 輸入資料緩衝器 65
5.2.4 印刷電路板 67
第6章結論與未來研究方向 68
6.1 結論 68
6.2 未來改進方向 68
參考文獻 69

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指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2010-11-17

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