博碩士論文 92541014 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:63 、訪客IP:3.15.0.212
姓名 莊青龍(Chin-Lung Chuang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 擁有全信號觀察能力的嵌入式測試向量加速技術
(Embedded Testbench Acceleration with Full Signal Visibility for Functional Verification)
相關論文
★ 運算放大器之自動化設計流程及行為模型研究★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器 之1.25-GHz八相位鎖相迴路★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 以現況來說,驗證仍然是IC設計流程中的主要瓶頸,當使用硬體輔助來加速模擬的方法以提升速度時,介於電腦主機與硬體加速器間額外產生的通信負擔,卻轉變成效能提升最大的障礙。此外,當設計放到硬體加速器之後,不良的信號觀察能力又是另一個除錯時令人頭痛的問題。因此,這篇論文將針對這兩個問題提出討論與解決方案。
在測試向量加速技術中,因為硬體和軟體分別放在不同的平台會造成額外的通訊負擔,使得舊有的方法不能兼顧效能與測試向量的相容性。因此,本論文提出了嵌入式測試向量加速技術,把原來會額外增加的通訊負擔降到最低,因此這個方法可以大幅的增加模擬的速度。本論文透過實際業界的例子加以實驗證明,我們的方法大約比業界的工具約快了十倍以上,不但如此,額外占用的硬體資源僅約百分之 0.57。由此可說明嵌入式測試向量加速技術是非常有效率的加速方式,卻又不需要占用太多昂貴的硬體資源。
另外,硬體原型平台在功能驗證中是極為重要的最後一個關卡,因為它擁有很高效率的運行速度,但是FPGA與生俱來的除錯能力卻非常之有限,因此,這篇論文提供另一個新穎的方法,即分段紀錄FPGA內部信號的狀態,並事後利用軟體模擬器撥放的方式,模擬出使用者想要觀察的區段信號。透過這個方法,我們仍然能夠擁有極高的運行速度,因為所有的運算已經由FPGA完成,而所有的信號仍然可以像軟體模擬器一樣被觀察到,大幅增加除錯的效率,最終也以實驗來驗證這個方法的優點。
摘要(英) Nowadays, verification is still a primary bottleneck in the design flow. While using the simulation acceleration techniques to speed up the simulation-based verification, the communication overhead between the host machine and accelerator often appears as an extra overhead that limits the obtained improvement. In addition, after the designs are put into the hardware-based accelerators, the poor visibility of internal signal becomes another issue while tracing the possible bugs. Therefore, the focuses of this dissertation are put on those two primary issues.
Due to the communication overhead between hardware and software, traditional simulation acceleration has to compromise between testbench compatibility and performance. In this dissertation, a new approach, named as Hybrid Embedded Testbench Acceleration (HETA), is proposed to reduce this communication overhead. This method can avoid the communication issue and greatly improve the simulation speed. Experimental results on an industry case show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator with only 0.57% hardware overhead. This demonstrated that HETA is an efficient solution to further reduce the simulation time for functional verification with less overhead.
Hardware prototype is very important in last stage of functional verification, due to its high simulation speed. However, it is very hard to debug using this approach due to poor visibility in the FPGA. Therefore, in this dissertation, propose another approach to “record” the internal behaviors of a FPGA and “replay” the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in the FPGA. Besides, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.
關鍵字(中) ★ 測試向量 加速 模擬 除錯 信號觀察 功能驗證 關鍵字(英) ★ emulation
★ simulation acceleration
★ testbench
★ signal visibility
★ prototype
★ debug
★ scan chain
★ functional verification
★ FPGA
論文目次 Chapter 1 Introduction - 1 -
1.1 Verification Bottleneck - 1 -
1.2 Existing Verification Approaches - 7 -
1.3 Communication Overhead in Simulation Acceleration - 13 -
1.4 Signal Visibility in Hardware- Based Prototyping - 18 -
1.5 Key Contributions - 20 -
1.6 Dissertation Organization - 22 -
Chapter 2 Hybrid Embedded Testbench Acceleration - 24 -
2.1 Related Works - 24 -
2.2 HETA Mechanism - 28 -
2.3 Hardware Implementation - 33 -
2.3.1 Event Detector - 34 -
2.3.2 Time Wheel Scheduler (TWS) - 34 -
2.3.3 Behavioral Testbench Processing Unit (BTPU)- 35 -
2.3.4 Synthesizable Behavioral Logic (SBL) - 37 -
2.3.5 Concurrent Function-slices Execution Controller (CFEC) - 38 -
2.3.6 Interface Signal Registers (ISR) - 38 -
2.3.7 Clock Controller - 39 -
2.4 Experimental Results - 40 -
2.5 Summary - 42 -
Chapter 3 Hybrid Approach for Visibility Improvement - 43 -
3.1 Motivation - 43 -
3.2 Snapshot and Reconstruction Mechanisms - 47 -
3.2.1 Recording Internal Behavior in a FPGA - 47 -
3.2.2 Waveform Reconstruction - 49 -
3.2.3 FPGA Implementation - 50 -
3.2.4 Snapshot for Embedded Memory - 53 -
3.3 Storage Data Reduction - 54 -
3.3.1 Some Observation for Reducing Storage Data - 54 -
3.3.2 Design Modeling Using S-Graph - 57 -
3.3.3 Translation of Node Selection Problem - 57 -
3.3.4 Modified Snapshot Mechanism - 58 -
3.4 Experimental Results - 60 -
3.5 Summary - 66 -
Chapter 4 Conclusions and Future Works - 68 -
Reference - 70 -
Publication List - 75 -
參考文獻 [1] K.-J. Kuhm, “Moore’s Law past 32nm: Future Challenges in Device Scaling,” International Workshop on Computational Electronics, pp. 1-6, May 2009
[2] Vince Emery Marketing Communications, “The Pentium Chip Story: A learning Experience,” http://www.emery.com/1e/pentium.htm
[3] P. Rashinkar, P. Paterson and L. Singh, “ System-on-a-chip Verification – Methodology and Techniques ,” Springer, December 2000
[4] Intel Corporation, “Validating the Intel Pentium 4 Microprocessor,” ftp://download.intel.com/technology/itj/q12001/pdf/art_3.pdf
[5] A. Molina and O. Cadenas, “Functional verification: approaches and challenges,” Scientific Electronic Library Online, December 2007
[6] A. Mulpur, “Use co-Simulation for the functional verification of RTL implementations,” Chip Design magazine, February 2002
[7] RoweBots Research Incorporation, “Time To Market,” http://www.rowebots.com/embedded_economics/ time_market
[8] A. Czamara, “SoCs require a new verification approach,” EE Times magazine, March 2005
[9] Skold, S. and Ayani, R., “Fast simulation of HDL models IEEE 1995,” IEEE Potentials, vol. 14, no. 5, pp. 14-17, January 1996
[10] S. Deniziak and K. Sapiecha, “High Level Testbench Generation for VHDL Models,” Engineering of Computer-Based Systems, pp.146-151, March 1999
[11] P. Heng, “A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models,” International Symposium on Quality Electronic Design, pp.456-459, March 2008
[12] Mentor Graphics, “Veloce emulation system,” http://www.mentor.com/ products /fv/emulation-systems/
[13] EVE, “ZeBu-XXL,” http://www.eve-team.com/products/zebu-xxl.php
[14] Cadence Design Systems, “Incisive Palladium series,” http://www.cadence.com/products/sd/palladium_series
[15] Cadence Design Systems, “Incisive Xtreme series,” http://www.cadence.com /products/fv/xtreme_series/Pages/default.aspx
[16] Accellera, “Standard Co-Emulation Modeling Interface Reference Manual,” http://www.eda.org/itc/scemi.pdf
[17] J. Andrews, “Modern simulation acceleration and emulation technology,” Cadence Design Systems, Incisive verification article, November 2005
[18] Altera Corporation, “SignalTap II Embedded Logic Analyzer,“ http://www.altera.com
[19] Xilinx Company, “ChipScope On Chip Debug Logic Analyzer,” http://www.xilinx.com
[20] Agilent Technologies, ”FPGA Dynamic Probe Data sheet ,” http://cp.literature.agilent.com/litweb/pdf/5989-0423EN.pdf
[21] IEEE standard, “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE standard 1149.1-2001
[22] C.-L. Chuang and C.-N. Jimmy Liu, “Hybrid Embedded Testbench Acceleration Technique for Reducing the Communication Overhead in Hardware-Accelerated Functional Verification,” to appear in IEEE Design and Test of Computers
[23] C.-L. Chuang, W.-H. Cheng, D.-J. Lu and C.-N. Jimmy Liu, “Hybrid Approach to Faster Functional Verification with Full Visibility,” IEEE Design and Test of Computers, vol. 24, no. 2, pp. 154-162, March 2007
[24] Aldec, “Riviera-PRO,” http://www.aldec.com”
[25] Y. Kim and C.-M. Kyung, “Tpartition: Testbench Partitioning for Hardware-Accelerated Functional Verification,” IEEE Design & Test of Computers, vol. 21, no. 6, pp. 494-502, November 2004
[26] H.-S. Choi, S.-B. Lee and S.-C. Park, “Instruction Based Testbench Architecture,” International Workshop System-on-Chip for Real-Time Applications, pp.329-333, July 2005
[27] Y. Kim and C.-M. Kyung, “Automatic Translation of Behavioral Testbench for Fully Accelerated Simulation,” International Conference on Computer Aided Design, pp. 218-221, November 2004
[28] I. Mavroidis and I. Papaefstathiou, “Efficient Testbench Code Synthesis for a Hardware Emulator System,” Design Automation & Test in Europe, pp. 888-893, April 2007
[29] R. Henftling, A. Zinn, M. Bauer, M. Zambaldi and W. Ecker, “Re-Use-Centric Architecture for a Fully Accelerated Testbench Environment,” Design Automation Conference, pp. 372-375, August 2003
[30] J. Bauer, M. Bershteyn, I. Kaplan and P. Vyedin “A Reconfigurable Logic Machine for Fast Event-Driven Simulation,” Design Automation Conference, pp 668-671, June 1998
[31] J. Andrews, “Keys to simulation acceleration and emulation success,” Cadence Design Systems, Incisive verification article, August 2005
[32] C.-H.-S. Ting, “Programming Embedded Systems in eForth,” O’reilly, 2003
[33] C.-L. Chuang and J.-E. Chen, “A FORTH System Implementation For Demonstration Of Hardware/Software co-desgn,” Chung Hua University master thesis, Taiwan, June 2000
[34] ARM, “ARM926EJ-S processor,” http://www.arm.com/products/CPUs /ARM926EJ-S.html
[35] ARM, “ARM1176 processor,” http://www.arm.com/products/CPUs /ARM1176.html
[36] A. Tiwari and K.-A. Tomko, “Scan-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs”, Asia and South Pacific Design Automation Conference, pp. 705-711, January 2003
[37] Xilinx Corporation, “Readback Function, XAPP138 : Virtex Configuration and Readback,” http://www.xilinx.com/ipcenter/catalog/search/reference/ xapp138_virtex_configuration_and_readback.htm
[38] A. Carbine and D. Feltham, “ Pentium-Pro processor design for test and debug,” IEEE Test Conference, pp. 294-303, November 1997
[39] T. Wheeler, P. Graham, B. Nelson, and B. Hutchings, “Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification”, International Conference on Field-Programmable Logic and Applications, August 2001
[40] B. Vermeulen and S. K. Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design and Test of Computers, vol. 19, no. 3, pp. 37-45, May 2002
[41] C.-L. Chuang, D.-J. Lu and C.-N. Liu, “A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA,” Asian Test Symposium, pp. 164-169, November 2004
[42] H.-M. Lin and J.-Y. Jou, “On Computing the Minimum Feedback Vertex Sets of a Directed Graph by Contraction Operations,” IEEE Transactions on Computer-Aided Design, vol. 19, no. 3, pp. 295-307, March 2000
[43] W.-H. Cheng, C.-L. Chuang and C.-N. Liu, “An Efficient Mechanism to Provide Full Visibility for Hardware Debugging,” International Symposium on Circuits and Systems, pp. 811-814, September 2006
[44] J. Marantz, “Enhanced Visibility and Performance in Functional Verification by Reconstruction,” Design Automation Conference, pp. 164-169, April 1998
[45] D. H. Lee and S. M. Reddy, “On Determining Scan Flip-Flops in Partial-Scan Designs,” International Conference on Computer Aided Design, pp. 322-325, November 1990
[46] R. Ashar and S. Malik, “Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications,” Design Automation Conference, pp. 76-80, March 1994
[47] S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algorithm for selecting partial scan flip-flops,” Design Automation Conference, pp. 81-86, March 1994
指導教授 劉建男(Chien-Nan Jimmy Liu) 審核日期 2011-1-4
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明