參考文獻 |
1. N. Savage, “Linking with light,” IEEE Spectr. vol. 39, no. 8, pp. 32–36, (2002)
2. B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Mahdavan, A. F. J. Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-processor with parallel multiwavelength optical interconnects,” IEEE J. Lightwave Technol., 22(9), 2043-2054 (2004)
3. S. Hiramatsu and T. Mikawa, “Optical design of active interposer for high-speed chip level optical interconnects,” IEEE J. Sel. Top. Quantum Electron., 24(2), 927-934 (2006)
4. M. Aljada, K. E. Alameh, Y. T. Lee, and I. S. Chung, “High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors,” Opt. Express, 14(15), 6823-6836 (2006)
5. X. Wang and R. T. Chen, “Fully embedded board level optical interconnects—From point-to-point interconnection to optical bus architecture,” Proc. SPIE, 6899, 6899031-6899039 (2008)
6. D. A. B. Miller, “Physical reasons for optical interconnection,” Int. J. Optoelectron., vol. 11, no. 3, pp. 155–168, (1997)
7. D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proceedings of the IEEE 88 (6), 728-749, (2000)
8. R. Ho, K. Mai, and M. Horowitz,“The Future of Wires,” Proceedings of the IEEE, pp. 490-504, Apr (2001)
9. J. Yeh, R. K. Kostuk, and K. Tu, “Hybrid free-space optical bus system for board-to-board interconnections,” Appl. Opt., vol. 35, no. 32, pp. 354–6364, (1996)
10. R. Heming, L. C. Wittig, P. Dannberg, J. Jahns, E. B. Kley, and M. Gruber, “Efficient planar-integrated free-space optical interconnects fabricated by a combination of binary and analog lithography,” IEEE J. Lightwave Technol., 26(14), 2136-2141 (2008)
11. P. Lukowicz et al., “Optoelectronic interconnection technology in the HOLMS system,” IEEE J. Sel. Top. Quantum Electron., 9(2), 624-635 (2003)
12. H. L. Althaus, W. Gramann, and K. Panzer, “Microsystems and wafer processes for volume production of highly reliable fiber optic components for telecom- and datacom-application,” IEEE Trans. on Compon., Packag., and Manufact. Technol. pt. B, 21(2), 147-156 (1998)
13. Jayakrishnan Chandrappan, “Performance Characterization Methods for Optoelectronic Circuit Boards,” IEEE J, vol. 1,no. 3, March (2011)
14. Xiaohui Lina, “Polymer Waveguide Arrary with 45 Degree Slopes Fabricated by Bottom Side Tilted Exposure,” SPIE Digital Library, Vol. 7944 794411-6(2011)
15. Roger Dangel,“Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications,“ IEEE J,vol. 31,no. 4(2008)
16. I. Zubel, “Silicon anisotropic etching in alkaline solutions III: On the possibility of spatial structures forming in the course of Si(100) anisotropic etching in KOH and KOH+IPA solutions,” Sens. Actuators, A, 84(1), 116-125 (2000)
17. H. C. Lan, H. L. Hsiao, C. C. Chang, C. H. Hsu, C. M. Wang, M. L. Wu, “Monolithic integration of elliptic-symmetry diffractive optical element on silicon-based 45° micro-reflector,” Opt. Express, 17(23), 20938-20944 (2009)
18. B. E. Lemoff, M. E. Ali, G. Panotopoulos, G. M. Flower, B. Mahdavan, A. F. J. Levi, and D. W. Dolfi, “MAUI: Enabling fiber-to-processor with parallel multiwavelength optical interconnects,” IEEE J. Lightwave Technol., 22(9), 2043-2054 (2004)
19. F. Wang, F. Liu, and A. Adibi, “45 degree polymer micromirror integration for board-level three-dimensional optical interconnects,” Opt. Express, 17(13), 10514-10521 (2009)
20. Graham T. Reed, and Andrew P. Knights, “Silicon Photonics,” Wiley(2004)
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