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姓名 蘇柏寬(Bo-kuan Su) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 三閘極金氧半場效電晶體之轉角效應探討
(Corner Effect in Triple-Gate MOSFET)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 本篇論文中，我們藉由二維元件模擬器探討三閘極金氧半場效電晶的元件特性，並探討因元件結構所產生的轉角效應，由於元件的電流大小與元件的通道寬度成正比，我們在元件通道的側壁上加上另外兩面閘極，以達到不降低電路密度而增加元件通道的有效寬度，提高元件的電流驅動力。從模擬結果中，三閘極結構比單閘極結構有著更好的電流驅動力。最後，我們將元件結構顯示器與載子濃度顯示器整合於二維元件模擬器當中，讓使用者可以更快速檢驗元件結構的正確性與快速觀察元件整體的載子分部情形。
摘要(英) In this thesis, we design a 2-D device simulator to simulate the triple-gate MOSFET device characteristic. Then discuss the corner effect of triple-gate structure. The triple-gate MOSFET has three surfaces of gate structures which can increase the effective channel width of the device to enhance the current drivability of the device without reducing the packing density of the circuit. According to the simulation results of the 2-D device, the saturation drain current of the triple-gate MOSFET are much better than the single-gate MOSFET. Finally, in order to quickly verify the device structure and simulation results, we design a 2-D structure and concentration indicator. The structure and concentration indicator can be used to quickly check the 2-D simulation results of the device structures and concentration result.
關鍵字(中) ★ 轉角效應
★ 三閘極
★ 元件模擬
★ 臨限電壓關鍵字(英) ★ Threshold voltage
★ simulation
★ Corner Effect
★ Triple-gate論文目次 摘要 I
ABSTRACT II
目錄 III
圖目錄 IV
表目錄 VI
第一章 簡介 1
第二章 結構與載子顯示器之二維元件模擬器 3
2-1二維等效模擬電路 3
2-2載子分佈與結構顯示器開發 5
2-3載子分佈與結構顯示器之應用 7
第三章 二維三閘極MOFET之轉角效應 11
3-1為何要做三閘極MOSFET 11
3-2載子分佈與轉角效應之探討 17
3-3臨限電壓與轉角效應之探討 21
第四章 三閘極MOSFET之二維模擬I-V量測 27
4-1通道等效電導之計算 27
4-2三閘極MOSFET之I-V特性 31
4-3三閘極與單閘極I-V特性之比較 34
第五章 結論 38
Reference 40
參考文獻 [1] D. Grant, “Power semiconductor devices-continuous development,” Microelectronics Journal, Volume 27, Issues 2-3 , pp. 161-176, March-June 1996.
[2] J. T. Park, J. P. Colinge and C. H. Diaz,“Pi-Gate SOI MOSFET,”IEEE Electron Devices Letters, VOL. 22, no. 8, August 2001.
[3] J. P. Colinge, M. H. Gao, A. Romano, H. Me and C. Claeys,“Silicon-on-Insulator Gate-All-Around MOS Device,”IEEE Transaction on Electron Devices, 1990, PP.137-138.
[4] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi., and K. Murase,“Ultimately thin double-gate SOI MOSFETs,”IEEE Transaction on Electron Devices, Volume： 50 Issue： 3 , March 2003,P.830-838.
[5] D. A. Neamen,“Semiconductor physics and devices,”3rd ed., McGraw-Hill Companies Inc., p536, 2003.
[6] B. P. Wong, A. Mittal, Y. Cao, and G. Star,“Nano-CMOS circuit and physical design,”by John Wiley & Son Inc., pp41-42, 2005.
[7] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Lbok, and M. R. Lin,“15nm gate length planar CMOS transistor,”in IEEE IEDM pp.937-939, Dec. 2001.
[8] Y. C. YEO, P. Ranade, Q. Lu, R. Lin, and T. J. King, C. Hu, “Effects of high-k dielectrics on the work-functions of metal and silicon gates,” in Symp. VLSI Technology, pp.49-50, June 2001.
[9] J. G. Fossum et al, “Suppression of Corner Effects in Triple-Gate MOSFETs,” IEEE Electron Device Letters, vol. 24, pp. 745-747, Dec 2003.
[10] R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Rios, T. Linton, R. Arghavani, B. Jin, S. Datta, and S. Hareland, “Advanced depleted-substrate transistors： Single-gate, double-gate, and tri-gate,” in Proc. Int. Conf. Solid State Devices and Materials, Sept.2002, pp. 68–69.
[11] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Tri-gate fully depleted CMOS transistors： Fabrication, design, and layout,” in Proc. VLSI Tech. Symp., June 2003, pp. 133–134.
指導教授 蔡曜聰(Yao-Tsung Tsai) 審核日期 2011-7-6 推文 plurk
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