| 姓名 |
趙盈勝(Ying-shang Chao)
查詢紙本館藏 |
畢業系所 |
電機工程學系在職專班 |
| 論文名稱 |
陣列區塊電容產生器於製程設計套件之評量
(Qualification of the Array-Block-Capacitance Creator for Process Design Kit)
|
| 相關論文 | |
| 檔案 |
 [Endnote RIS 格式]
[Bibtex 格式]
 [相關文章]  [文章引用]  [完整記錄]  [館藏目錄]  至系統瀏覽論文 ( 永不開放)
|
| 摘要(中) |
在類比/混頻電路(Analog/Mixed-Mode circuit)的先進製程中，為加快設計流程(Design Flow)與提高產品開發的成功率，設計者需直接使用晶圓代工廠(Foundry)提供之製程設計套件(PDK)做電路設計(Circuit design )、模擬(Simulation)與佈局(Layout)。製程設計套件(PDK)為晶圓代工廠，依該製程之特性並收集生產線上開發製程時，所累積經驗與整合使用者需求而來。製程設計套件(PDK)亦需晶圓代工廠與電子設計自動化 (EDA)廠商密切合作，以將各功能包裹進使用者使用之開發環境。
另在類比/混頻電路(Analog/Mixed-Mode circuit)中，我們常需考慮電路中，元件的匹配度問題以提高電路效能；但卻考慮不到，這些需高度匹配的元件在晶圓實際製程流程中，遇到的製程變動問題，可能降低元件匹配度。
故我們引入陣列區塊電容產生器(Array-Block-Capacitance Creator)，即以啟發式演算法(Heuristic Algorithm)做陣列區塊電容之佈置，再利用統計學之空間相關性模型(Spatial-Correlation Model)做評估，最後再藉設計製程套件(PDK)的開發流程，評量如何將其內建於現有設計製程套件(PDK)中，藉此提供類比/混頻電路(Analog/Mixed-Mode circuit)在設計佈局(Layout)時最佳解法。
|
| 摘要(英) |
In Analog/Mixed-mode advance process, designer need use Process Design Kit to speed up the design flow and to enhance the success of product development. “Process Design Kit” is provided and verified by Foundry, it included the properties of the specified process, collecting the experience while process development, and integrate user’s request. “Process Design Kit” needs closer cooperation within Foundry and EDA vendor.
In Analog/Mixed-mode circuit, we also need consider about the device matching to keep the performance of the circuit. But it’s not easy to predict and control the device matching while the devices in foundry’s process. Because the process variation affects the device character and reduces the device matching.
We use Heuristic algorithm to get the placements, and find-out the optimal placement by considering the spatial correlation model which comes from Statistic. These procedures provided us a good solution, “Array-Block-Capacitance Creator”. By qualified our solution within PDK provider’s development flow and user’s design flow, we could embedded and used it in current PDK.
|
| 關鍵字(中) |
★ 陣列區塊電容產生器
★ 製程設計套件 |
關鍵字(英) |
★ Array-Block-Capacitance Creator
★ Process Design Kit
★ PDK
★ FDK |
| 論文目次 |
目錄
摘 要 II
Abstract III
誌謝 IV
目錄 V
圖目錄 VI
表目錄 VIII
第一章 簡介 1
第二章 製程設計套件 3
2-1 製程設計套件定義 3
2-2製程設計套件內容 5
2-3 製程設計套件使用流程 11
2-4製程設計開發流程 18
2-5 製程設計驗證內容 21
第三章 陣列區塊電容產生器 25
3-1 空間相關性有關之統計學名詞定義 25
3-1-1 母體(Population) 25
3-1-2 樣本(Sample) 25
3-1-3 平均值(mean, μ) 25
3-1-4 變異數(Variance, σ2) 25
3-1-5 標準差(Standard Deviation, σ) 26
3-1-6 變異係數(Coefficient of Variation, cv) 26
3-1-7 共變異數(Co-Variance, σxy) 26
3-1-8 相關係數(Correlation Coefficient, ρxy) 27
3-1-9 常態分佈(Normal Distribution) 28
3-2電容的空間相關性模型 29
3-4 陣列區塊電容產生器 33
3-4-1 陣列區塊電容產生器之概念 33
3-4-2 陣列區塊電容產生器之步驟 34
第四章 驗證流程 40
第五章 結論 47
參考文獻 48
|
| 參考文獻 |
[1] “Deploying Interoperable Pcell Libraries,” IPL now.com Jane, 2007.
[2] S. Nassif, “Modeling and analysis of manufacturing variations,” IEEE Conference on Custom Integrated Circuits, pp. 223-228, 2001.
[3] M. J. M. Pelgrom, and A. P. G. Welbers, “Matching Properties of MOS Transistors” IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989.
[4] Wenshu chang, “Introduction of T13RF PDK”, CICeNews Vol. 67, May, 2006.
[5] “65 Nanometer- Customer-Driven Foundry Solution “ www.umc.com, 2011
[6] P-W. Lou, J-E. Chen, C-L Wey, L-C. Cheng, J-J. Chen, and W-C. Wu. Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems 2008; 27: 2097-2101
[7] J-E. Chen, P-W. Lou, C-L Wey. Yield Evaluation of Analog Placement with Arbitrary Capacitance Ratio. Proc. International Symp. On Quality Electric Design 2009:179-184
[8] P-W. Lou, J-E. Chen, C-L Wey, Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
[9] A. Stuart, J.K. Ord. Kendall’s Advanced Theory of Statistics. Oxford University Press：New York,1987：320-325
[10] P-W. Lou, J-E. Chen, C-L Wey, Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits
[11] “OA PDK Training – How to Build PDK in Laker QA” SpringSoft
[12] 曾煥程, “應用於電容陣列區塊之維持比值良率的通道繞線法”，國立中央大學電機工程學系碩士論文, 2010.
|
| 指導教授 |
陳竹一(Jwu-e Chen)
|
審核日期 |
2011-11-30 |
| 推文 |
 facebook  plurk  twitter  funp  google  live  udn  HD  myshare  reddit  netvibes  friend  youpush  delicious  baidu
|
| 網路書籤 |
 Google bookmarks  del.icio.us  hemidemi myshare
|
