參考文獻 |
[1] H.-J. Hsu, and S.-Y. Huang, ‘‘A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme,’’ IEEE Trans. on VLSI, vol. 19, no. 1, pp. 165-170, Jan. 2011.
[2] W. Liu, W. Li, P. Ren, C. Lin, S. Zhang, and Y. Wang, “A PVT tolerant 10 to 500 MHz all-digital phase-locked loop with coupled TDC and DCO,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 314-321, Feb. 2010
[3] C.-C. Hung, and S.-I. Liu, ‘‘A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm,’’ IEEE Trans. on Circuits Syst. II: Expr. Briefs, vol. 58, no. 6, pp. 321-325, Jun. 2011.
[4] T. Tokairin, M. Okada, M. Kitsunezuka, T. Maeda, and M. Fukaishi ‘‘A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter,’’ IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2582-2590, Oct. 2010.
[5] M. S.-W. Chen, D. Su, and S. Mehta, ‘‘A calibration-free 800 MHz fractional-N digital PLL with embedded TDC,’’ IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2819 - 2827, Oct. 2010.
[6] H.-Y. Huang, and F.-C. Tsai, ‘‘Analysis and optimization of ring oscillator using sub-feedback scheme,’’ in Proc. IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems, Apr. 2009, pp. 28-29.
[7] M. Lee, and A. A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr. 2008.
[8] V. Kratyuk, ‘‘Digital phase-locked loops for multi-GHz clock generation,” OSU Ph. D. Thesis, Dec. 2006.
[9] S.-Y. Lin, and S.-I. Liu, “A 1.5 GHz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111-3119, Nov. 2009.
[10] Y.-H. Seo, S.-K. Lee, and J.-Y. Sim, “A 1-GHz digital PLL with a 3-ps resolution floating-point-number TDC in a 0.18-um CMOS” IEEE Trans. on Circuits Syst. II: Expr. Briefs, vol. 58, no. 2, pp. 70-74, Feb. 2011.
[11] H.-J. Hsu, C.-C. Tu, and S.-Y. Huang, “A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory”, IEEE Symposium on VLSI-DAT, Apr. 2008.
[12] W. Grollitsch, R. Nonis, and N. D. Dalt, ‘‘A 1.4 psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS,’’ in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 478-479.
[13] M. Lee, M.-E. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808-2816, Oct. 2009.
[14] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, ‘‘A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,’’ IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008.
[15] M. Z. Straayer, and M. H. Perrott, ‘‘A multi-path gated ring oscillator TDC with first-order noise shaping,’’ IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, Apr. 2009.
[16] S.-K. Lee, Y.-H. Seo, H.-J. Park, and J.-Y. Sim, ‘‘A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 um CMOS,’’ IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2874-2881, Oct. 2010.
[17] P. Lu, and H. Sjoland, ‘‘A 5GHz 90-nm CMOS all digital phase-locked loop,’’ IEEE Asian Solid-State Circuits Conference, pp. 65-68, Dec. 2009.
[18] V. Kratyuk, P.-K. Hanumolu, K. Ok, U.-K. Moon, and K. Mayaram, ‘‘A digital PLL with a stochastic time-to-digital converter,’’ IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 8, pp. 1612-1621, Dec. 2008.
[19] V. D. Heyn, G. Van der Plas, J. Ryckaert, and J. Craninckx, ‘‘A fast start-up 3GHz–10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS,’’ ESSCIRC Solid State Circuits Conference, pp. 484-487, Jan. 2008.
[20] R.K. Pokharel, A. Tomar, H. Kanaya, and K. Yoshida, ”Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process”, China-Japan Joint Microwave Conference, Sep. 2007.
[21] B. Tong, W. Yan, and X. Zhou, “A Constant-Gain Time-Amplifier with Digital Self-Calibration”, IEEE International Conference on ASIC, pp. 1133–1136, Oct. 2009.
[22] K.-H. Cheng, C.-C. Hu; J.-C. Liu, and H.-Y. Huang, ‘‘A Time-to-Digital Converter Using Multi-Phase-Sampling and Time Amplifier for All Digital Phase-Locked Loop,’’ IEEE Symposium on DDECS, pp. 285-288, Jun. 2010.
[23] S.-I. Liu, and C.-Y. Yang, ‘‘Phase-locked loop,’’ Taipei: Tsang Hai Book Publishing Co., Nov. 2006.
[24] F.-C. Tasi, ‘‘Interpolation multiphase phase locked loop,” NTPU M. Thesis, Jul. 2009.
[25] U.-J. Chen, ‘‘An ultra low power all digital PLL for wide power supply range,” NCU M. Thesis, Oct. 2009.
[26] Y.-L. Chang, ‘‘An 1.25-GHz all digital phase-Locked loop for low supply voltage applications,” NCU M. Thesis, Oct. 2010.
|