雙閘極金氧半場效電晶體與電路應用

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：35

、訪客IP：3.23.92.64

姓名

洪書群(Shu-chun Hung) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

雙閘極金氧半場效電晶體與電路應用
(A Study of Dual-Gate MOSFET and Its Applications)

相關論文

★ 電子式基因序列偵測晶片之原型	★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用
★ 使用覆晶技術之微波與毫米波積體電路	★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析
★ 以標準CMOS製程實現之850 nm矽光檢測器	★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計
★ 具有低摻雜Ｐ型緩衝層與穿透型Ｐ＋射源結構之600V穿透式絕緣閘雙極性電晶體	★ 空乏型功率金屬氧化物半導體場效電晶體設計、模擬與特性分析
★ 高頻氮化鋁鎵/氮化鎵高速電子遷移率電晶體佈局設計及特性分析	★ 氮化鎵電晶體 SPICE 模型建立與反向導通特性分析
★ 加強型氮化鎵電晶體之閘極電流與電容研究和長時間測量分析	★ 新型加強型氮化鎵高電子遷移率電晶體之電性探討
★ 氮化鎵蕭特基二極體與高電子遷移率電晶體之設計與製作	★ 整合蕭特基p型氮化鎵閘極二極體與加強型p型氮化鎵閘極高電子遷移率電晶體之新型電晶體
★ 垂直型氧化鎵蕭特基二極體於氧化鎵基板之製作與特性分析	★ 氮化鋁鎵/氮化鎵高電子遷移率電晶體之佈局分析及功率放大器研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

本論文將著重在雙閘極金氧半場效電晶體(Dual-Gate MOSFETs)的特性分析與量測，其包括了直流量測(DC I-V)、小訊號S參數(S-parameters)、大訊號負載拉移(Load-Pull Measurement)、低頻雜訊量測(Flicker Noise)以及高頻雜訊量測(High Frequency Noise)。因雙閘極電晶體擁有兩個閘極，論文中也會將不同閘極長度(Gate Length)組合而成的電晶體做特性比較。其中本文也替雙閘極金氧半場效電晶體建立對應之模型以利預測元件特性，並將量測與模擬結果作比較驗證。最後再將雙閘極金氧半場效電晶體應用於低雜訊放大器(Low-Noise Amplifier)與壓控振盪器(Voltage-Controlled Oscillator)。

摘要(英)

The dual-gate MOSFETs having two independent gates with the same body P-well layer have been analyzed in this thesis. The characteristics including DC I-V, S-parameters, and the large-signal behavior using load-pull system were measured to realize the performance improvement. Flicker noise and high-frequency noise depending on the gate and body biases are also investigated in different gate lengths of dual-gate MOSFETs. Furthermore, a small-signal equivalent dual-gate model is established to verify the small- and large-signal characteristics of the proposed model as well. Two RF circuits, 5 GHz low-noise amplifier and 9 GHz voltage-controlled oscillator, are also designed by using the proposed large-signal model stacking two MOSFETs in cascode. The measured results show that the performances of the dual-gate circuits can be accurately predicted by employing the proposed model.

關鍵字(中)

★ 雙閘極

關鍵字(英)

★ dual gate

論文目次

中文摘要 IV
英文摘要. V
致謝 VI
目錄 VII
圖目錄 IX
表目錄 XII
第一章導論 1
1.1 研究動機. 1
1.2 研究背景. 2
1.3 論文架構. 4
第二章雙閘極金氧半場效電晶體特性模擬、量測 5
2.1 單閘極、雙閘極金氧半場效電晶體與疊接結構. 5
2.1.1 單閘極金氧半場效電晶體 5
2.1.2 疊接結構組態 11
2.1.3 雙閘極金氧半場效電晶體 13
2.1.4 元件佈局圖 15
2.2 雙閘極金氧半電晶體直流特性. 18
2.2.1 外接基極電阻所衍生的效應 23
2.3 雙閘極金氧半電晶體小訊號特性. 26
2.4 雙閘極金氧半電晶體大訊號特性. 31
2.5 雙閘極金氧半場效電晶體模型建立. 34
2.6 結論. 39
第三章雙閘極金氧半場效電晶體雜訊特性 41
3.1 低頻雜訊簡介. 41
3.2 低頻雜訊量測結果. 43
3.3 高頻雜訊簡介. 46
3.4 高頻雜訊量測結果. 47
3.5 結論. 51
第四章雙閘極電晶體應用於低雜訊放大器及振盪器 52
4.1 低雜訊放大器. 52
4.1.1 電路設計與模擬 53
4.1.2 電路量測結果 58
4.2 壓控振盪器. 63
4.2.1 電路設計與模擬 65
4.2.2 電路量測結果 68
4.3 結論. 72
第五章結論 73
參考文獻 75
附錄A 口試問題與回答 . 79

參考文獻

[1] Quay, R.; Tessmann, A.; Kiefer, R.; Maroldt, S.; Haupt, C.; Nowotny, U.; Weber, R.; Massler, H.; Schwantuschke, D.; Seelmann-Eggebert, M.; Leuther, A.; Mikulla, M.; Ambacher, O., “Dual-Gate GaN MMICs for MM-Wave Operation,” IEEE
Microwave and Wireless Components Letters, Vol. 21, No. 2, February 2011.
[2] Narasimhamurthy, K.C.; Paily, R.; "Performance Comparison of Single- and Dual-Gate Carbon-Nanotube Thin-Film Field-Effect Transistors," IEEE Transactions on Electron Devices, Vol. 58, No. 7, July 2011.
[3] Hong-Yeh Chang; Kung-Hao Liang; "A 0.18 um Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits," IEEE TRANSACTIONS ON Microwave Theory and Techniques, Vol. 59, No. 1, January 2011.
[4] Fujimoto, R.; Kojima, K.; Otaka, S.; "A 7-GHz 1.8-dB NF CMOS Low-Noise Amplifier," IEEE Journal of Solid-State Circuits, Vol. 37, No. 7, July 2002.
[5] 林昀; "電子學" 鼎茂出版 2003.
[6] Behzad Razavi; "Design of Analog CMOS Integrated Circuits," McGraw-Hill, International Edition 2001.
[7] Bouhana, E.; Scheer, P.; Boret, S.; Gloria, D.; Dambrine, G.; Minondo, M.; Jaouen, H.; "Analysis and modeling of substrate impedance network in RF CMOS," IEEE
International Conference on Microelectronic Test Structures, 2006.
[8] F. Curp. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, "Impact of Interfacial Layer on the Low-Frequency Noise(1/f) Behavior of MOSFETs With Advanced Gate Stacks," IEEE Electron Device Letters, Vol. 27, NO. 8, August, 2006.
[9] M. G. Peters and J. I. Dijkhuis, "Random telegraph signals and 1/f noise in a silicon quantum dot," Journal of Applied Physics, Vol. 86, NO. 3, August, 1999.
[10] Philippe Gaubert, Akinobu Teramoto, Weitao Cheng, and Tadahior Ohmi, "Relation Between the Mobility, 1/f Noise, and Channel Direction in MOSFETs Fabricated on (100) and (110) Silicon-Oriented Wafers," IEEE Transactions on
Electron Devices, Vol. 57, NO.7, July, 2010.
[11] Ostling, Mikael .et all .“Low-frequency Noise in Advanced MOS Devices”, springer, 2007
[12] Kwok K Hung, Ping K.Ko, Chen ming Hu, Yiu C.Cheng.“A Unified Model for the Flicker Noise in Metal Oxide-Semiconductor Field- Effect Transistors”, IEEE Transaction on Electron Device, VOL. 37, pp. 654-665, 1900
[13] Maisurah, S.; Wong Sew Kin; Kung, F.; See Jin Hui; "0.18 μ m CMOS Low Noise Amplifier for 3-5GHz Ultra-Wideband System," International Symposium on Integrated Circuits, 2007.
[14] Lu Huang; Lisong Feng; Fujiang Lin; "A 0.18 μm CMOS 3–5GHz switched gain low noise amplifier for UWB system," IEEE International Symposium on Radio-Frequency Integration Technology, 2009.
[15] Meaamar, A.; Boon Chirn Chye; Do Man Anh; Yeo Kiat Seng; "A 3–8 GHz Low-Noise CMOS Amplifier," IEEE Microwave and Wireless Components Letters, Vol. 19, No. 4, April 2009.
[16] Sapone, G.; Palmisano, G.; "A 3–10-GHz Low-Power CMOS Low-Noise Amplifier for UWB Communication," IEEE Transactions on Microwave Theory and Techniques, Vol. 59, No. 3, March 2011.
[17] Bonghyuk Park; Seungsik Lee; Sangsung Choi; Songcheol Hong; "A 12-GHz Fully Integrated Cascode CMOS LC VCO With Q-Enhancement Circuit," IEEE Microwave and Wireless Components Letters, Vol. 18, No. 2, February 2008.
[18] Siprak, D.; Tiebout, M.; Zanolla, N.; Baumgartner, P.; Fiegna, C.; "Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias," IEEE Journal of Solid-State Circuits, Vol. 44, No. 7, July 2009
[19] Jonghae Kim; Plouchart, J.-O.; Zamdmer, N.; Trzcinski, R.; Kun Wu; Gross, B.J.; Moon Kim; "A 44GHz differentially tuned VCO with 4GHz tuning range in 0.12 μm SOI CMOS," IEEE International Solid-State Circuits Conference, 2005.
[20] Donghyun Baek; Taeksang Song; Euisik Yoon; Songcheol Hong; "8-GHz CMOS quadrature VCO using transformer-based LC tank," IEEE Microwave and Wireless Components Letters, Vol. 13, No. 10, October 2003
[21] Sangsoo Ko; Jeong-Geun Kim; Taeksang Song; Euisik Yoon; Songcheol Hong; "20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers," IEEE Radio Frequency Integrated Circuits Symposium, 2004.
[22] Nam-Jin Oh; Sang-Gug Lee; "11-GHz CMOS differential VCO with back-gate transformer feedback," IEEE Microwave and Wireless Components Letters, Vol. 15, No. 11, November 2005.
[23] C. W. Kuo, C. C. Hsiao, C. C. Ho, and Y. J. Chan, “Scalable large-signal model of 0.18 μm CMOS process for RF power predictions,”Solid State Electron., vol. 47, pp. 77–81, 2002.

指導教授

辛裕明(Yue-ming Hsin)

審核日期

2012-2-2

推文