雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製

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陳汜華(Si-Hua Chen) 查詢紙本館藏

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電機工程學系

論文名稱

雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
(Dual-gate Device Modeling and Microwave/Millimeter-Wave Distributed Amplifier Design)

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摘要(中)

在通訊與多媒體的快速發展之下，對於高傳輸速率與高容量傳輸系統的需求也愈來愈高。隨著高傳輸速率的無線通訊市場的大量增加，積體電路設計的操作頻率也逐漸往微波與毫米波頻段發展。
論文第一章將簡短介紹射頻發射機與光通訊系統的傳輸系統。第二章第一部份先整理1970年迄今介紹FET等效小訊號模型的相關文獻，將單閘極元件模型歸納為7種主要類型。第二部份整理歷年來介紹關於雙閘極元件等效小訊號模型的文獻，歸納為4種主要小訊號模型，而雙閘極元件由於可以等效為兩個單閘極元件疊接，因此可以設計應用在高增益及寬頻的系統上。為了驗證單閘極及雙閘極元件模型，將於第三章應用第二章介紹的模型萃取方法，以砷化鎵0.5 μm增強/空乏模式電晶體元件進行設計及量測，分別重建2組單閘極小訊號模型與1組雙閘極元件模型。
西元1948年E. L. Ginzton提出的分佈式放大器，由於擁有高增益頻寬比，因此在寬頻放大器的應用上佔有舉足輕重的地位。第四章以一組雙閘極與單閘極元件進行疊接架構作為增益單元，應用電感提升與m衍生低通濾波器技術來增加高頻增益，最後再應用主動負載提供偏壓來減少直流功率損耗。第五章以砷化鎵0.5 μm HBT-HEMT製程設計一組以HEMT-HBT串接達靈頓對為增益單元，半電路為串聯單級分佈式放大器的差動達靈頓串聯單級分佈式放大器。相較於半電路為傳統式分佈式放大器的差動放大器，使用串聯單級分佈式放大器作為差動放大器的半電路能擁有更佳的共模拒斥比特性。第六章第一部份使用矽金氧半場效電晶體的0.18 μm SiGe BiCMOS製程，以NMOS與HBT兩種不同電晶體作為增益單元，應用疊接架構來降低輸入端等校雜散電容，並減少米勒效應(Miller effect)對電路的影響，最後設計出一組高頻寬的傳統分佈式放大器。由於串聯單級分佈式放大器的輸出功率受限於輸出端電晶體的大小，因此在第二部分使用矽金氧半場效電晶體的90 nm CMOS製程，以傳統分佈式放大器作為串聯單級分佈式放大器的輸出級電路來增加串聯單級分佈式放大器的輸出功率，設計出一組CSSDA-CDA組合式分佈式放大器。第七章為結論，為本論文所做的研究做一個總結。

摘要(英)

The demands for high-speed and high-capacity transmission systems rapidly increase due to the development of multimedia communications in recent years. The increasing trend in modern wireless communications for high data-rate applications, especially for the analog and RF front-end is pushing the integrated circuits to operate in microwave and millimeter wave.
In this thesis, the introductions of RF transceiver and optical communication are given in Chapter 1. Since the device model of single-gate and dual-gate FETs are essential in the design of microwave circuits, seven kinds of single-gate small signal model and four kinds of dual-gate small signal model are generalized in Chapter 2. To analyze the characteristics of a 0.5 μm enhancement/depletion-mode (E/D-mode) GaAs process, two single-gate and a dual-gate small signal models based on the method introduced in Chapter 2 have been presented in Chapter 3.
The distributed amplifier (DA) is well known to be a good topology for ultra-wideband design after it was proposed by E. L. Ginzton in 1948. In Chapter 4, two conventional DAs with inductive peaking and m-derived technique, and a cascode configuration with a single-gate device and a dual-gate device is adopted for the gain cell to have the property of wideband and over 10 dB small-signal gain. An active load technique is used for the DC bias of the DA design to achieve low DC consumption. A Darlington differential cascaded single-stage DA (CSSDA) using a GaAs 0.5-μm HBT-HEMT process is presented in Chapter 5. To compare with the conventional DA (CDA), the CSSDA topology has better common-mode rejection ratio. To achieve the broadband design, two DAs with inductive peaking technique using Si-based process are presented in Chapter 6. In the first section, a CDA using 0.18 μm SiGe BiCMOS process and a cascode NMOS-HBT topology is used for the gain cell to decrease the Miller effect. The proposed DA has an average small-signal gain of 8.2 dB and a 3-dB bandwidth from DC to 31 GHz. To improve the output power of the CSSDA, a CSSDA-CDA composite DA using 90 nm CMOS process has been presented in the second section of Chapter 6. Finally, the conclusion is given in Chapter 7.

關鍵字(中)

★ 雙閘極元件
★ 分佈式放大器
★ 差動放大器
★ 串聯單級分佈式放大器

關鍵字(英)

★ dual-gate
★ distributed amplifier (DA)
★ differential amplifier
★ cascaded single-stage DA (CSSDA)

論文目次

中文摘要 I
Abstract III
誌謝 V
目錄 VIII
圖目錄 XIII
表目錄 XXI
第一章緒論 1
1.1 研究動機 1
1.2 相關研究發展 4
1.3 論文貢獻 5
1.4 論文架構 5
第二章單閘極與雙閘極高速電子遷移率電晶體小訊號等效電路萃取方法文獻整理回顧 7
2.1 簡介 7
2.2 單閘極電晶體小訊號等效電路模型與參數萃取 9
2.2.1 早期小訊號等效電路模型 9
2.2.1.1 Wolf小訊號等效電路模型 9
2.2.1.2 Liechti－Minasian小訊號等效電路模型 10
2.2.2 小訊號等效電路模型 14
2.2.2.1 Dambrine et al.小訊號等效電路模型[8] 14
2.2.2.2 Hughes-Tasker小訊號等效電路模型[12] 15
2.2.2.3 Arnold et al.小訊號等效電路模型[10] 16
2.2.2.4 Berroth-Bosch小訊號等效電路模型[11] 17
2.2.2.5 Vickes小訊號等效電路模型[13] 19
2.2.2.6 Anholt-Swirhun小訊號等效電路模型[14] 20
2.2.2.7 Kompa-Novotny小訊號等效電路模型[15] 21
2.2.3 參數萃取流程簡介 22
2.2.4 外部寄生元件等效電路模型與參數萃取（冷偏壓模態） 24
2.2.4.1 冷偏壓模態通道導通 24
2.2.4.1.1 第一類型外部寄生元件 24
2.2.4.1.2 第二類型外部寄生元件 25
2.2.4.1.3 第三類型外部寄生元件 25
2.2.4.1.4 冷偏壓通道導通模型外部寄生元件歸納 26
2.2.4.2 冷偏壓模態通道夾止 27
2.2.4.2.1 Dambrine et al.冷偏壓通道夾止模型[8] 27
2.2.4.2.2 White-Healy冷偏壓通道夾止模型[58] 28
2.2.4.2.3 Tayrani et al.冷偏壓通道夾止模型[57] 30
2.2.4.2.4 Stiebler et al.冷偏壓通道夾止模型[80] 31
2.2.4.2.5 Ooi-Ma冷偏壓通道夾止模型[62] 33
2.2.4.2.6 冷偏壓通道夾止模型外部寄生元件歸納 35
2.2.5 內部本質元件參數萃取（熱偏壓模態） 36
2.2.5.1 第一類型內部本質元件 36
2.2.5.2 第二類型內部本質元件 38
2.2.5.3 第三類型內部本質元件 39
2.2.5.4 第四類型內部本質元件 41
2.2.5.5 熱偏壓模態內部本質元件歸納 43
2.3 雙閘極電晶體小訊號等效電路模型與參數萃取 43
2.3.1 雙閘極小訊號電路等效模型 44
2.3.1.1 Asai et al.雙閘極小訊號等效電路模型（型1） 44
2.3.1.2 Tsironis-Meierer雙閘極小訊號等效電路模型（型2） 45
2.3.1.3 Kim雙閘極小訊號等效電路模型（型3） 46
2.3.1.4 Langrez et al.雙閘極小訊號等效電路模型（型4） 47
2.3.2 參數萃取流程簡介 48
2.3.3 外部寄生元件參數萃取（冷偏壓模態） 49
2.3.3.1 冷偏壓模態通道夾止 49
2.3.3.2 冷偏壓模態通道導通 50
2.3.3.2.1 外部寄生電阻與級間電阻 50
2.3.3.2.2 外部寄生電感[29] 54
2.3.4 內部本質元件參數萃取（熱偏壓模態） 54
2.3.4.1 忽略R12-Scott-Minasian雙閘極內部元件模型[24] 54
2.3.4.2 考慮R12-Ibrahim et al.雙閘極內部元件模型[28] 57
2.4 結論 61
第三章單閘極與雙閘極假晶格(Pseudomorphic)高速電子遷移率電晶體之小訊號模型建立 64
3.1 簡介 64
3.2 單閘極增強型與空乏型電晶體小訊號模型建立 64
3.2.1 單閘極元件參數 64
3.2.2 冷偏壓模態(Cold mode)外部參數萃取 67
3.2.2.1 冷偏壓模態通道導通VGS＞Vth 67
3.2.2.2 冷偏壓模態通道夾止VGS＜Vp 78
3.2.3 熱偏壓模態(Hot mode)內部參數萃取 80
3.2.4 模型建立結果 86
3.2.5 比例規則(Scaling Factors Rules) 90
3.3 雙閘極增強/空乏型電晶體小訊號模型建立 91
3.3.1 雙閘極元件參數 91
3.3.2 冷偏壓模態(Cold mode)外部參數萃取 95
3.3.2.1 冷偏壓模態通道導通VGS＞Vth 95
3.3.2.2 冷偏壓模態通道夾止VGS＜Vp 102
3.3.3 增強/空乏型雙閘極內部參數 106
3.3.4 模型建立結果 106
3.4 結論 109
第四章雙閘極疊接分佈式放大器設計 110
4.1 簡介 110
4.2 雙閘極疊接分佈式放大器設計概念 111
4.2.1 傳統分佈式放大器[33][84] 111
4.2.2 常數k與m衍生濾波器技術 116
4.2.3 主動式負載 122
4.3 雙閘極疊接分佈式放大器設計流程 124
4.3.1 增益單元的設計 124
4.3.2 m衍生濾波器與電感提升技術的設計 125
4.3.3 主動式負載的設計 127
4.3.4 設計流程圖 128
4.4 雙閘極疊接分佈式放大器模擬結果與佈局 129
4.4.1 六級雙閘極疊接分佈式放大器模擬結果與佈局圖 129
4.4.2 八級雙閘極疊接分佈式放大器模擬結果與佈局圖 133
4.5 雙閘極疊接分佈式放大器量測結果 136
4.5.1 六級雙閘極疊接分佈式放大器量測結果 136
4.5.2 八級雙閘極疊接分佈式放大器量測結果 140
4.6 結論 145
第五章差動達靈頓對串聯單級分佈式放大器設計 147
5.1 簡介 147
5.2 差動達靈頓對串聯單級分佈式放大器設計概念 148
5.2.1 HBT-HEMT製程介紹 148
5.2.2 串聯單級分佈式放大器 149
5.2.3 達靈頓對 150
5.2.4 電流源 151
5.2.5 共模拒斥比(CMRR) 151
5.3 差動達靈頓對串聯單級分佈式放大器設計流程 152
5.3.1 增益單元的設計 152
5.3.2 電流源的設計 154
5.3.3 設計流程圖 154
5.4 差動達靈頓對串聯單級分佈式放大器模擬結果與佈局 156
5.4.1 混合模式(Mixed-Mode) 157
5.4.2 單端輸入-輸出模式(Single-ended–Single-ended Mode) 161
5.4.3 電路佈局圖 162
5.5 差動達靈頓對串聯單級分佈式放大器量測結果 163
5.5.1 混合模式(Mixed-Mode) 164
5.5.2 單端輸入-輸出模式(Single-ended–Single-ended Mode) 168
5.5.3 實作晶片圖與量測眼圖 169
5.6 結論 172
第六章應用互補式金屬氧化物半導體製程設計分佈式放大器 173
6.1 簡介 173
6.2 雙載子互補式金氧半電晶體疊接分佈式放大器 174
6.2.1 台積電0.18 μm SiGe BiCMOS製程技術 174
6.2.2 雙載子互補式金氧半電晶體疊接分佈式放大器設計概念 174
6.2.3 雙載子互補式金氧半電晶體疊接分佈式放大器設計流程 177
6.2.3.1 疊接架構的選擇 177
6.2.3.2 級數的選擇 178
6.2.3.3 m衍生T接面低通濾波器 178
6.2.3.4 主動式負載的選擇 179
6.2.3.5 設計流程圖 179
6.2.4 雙載子互補式金氧半電晶體疊接分佈式放大器模擬結果與佈局 180
6.2.5 雙載子互補式金氧半電晶體疊接分佈式放大器量測結果與除錯 184
6.2.5.1 量測結果 184
6.2.5.2 電路除錯 188
6.2.6 文獻比較表 196
6.3 組合分佈式放大器 197
6.3.1 台積電90 nm CMOS製程技術 197
6.3.2 組合分佈式放大器設計概念 197
6.3.3 組合分佈式放大器設計流程 198
6.3.3.1 m衍生T接面低通濾波器 198
6.3.3.2 串聯單級分佈式放大器設計 198
6.3.3.3 傳統分佈式放大器設計 200
6.3.3.4 設計流程圖 203
6.3.4 組合分佈式放大器模擬結果與佈局 204
6.3.5 組合分佈式放大器量測結果與除錯 207
6.3.5.1 量測結果 207
6.3.5.2 電路除錯 212
6.3.6 文獻比較表 219
6.4 結論 220
第七章結論 221
參考文獻 223

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指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2012-8-21

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