適用於800 MHz ~ 1.6 GHz具快速鎖定之全數位脈波寬度控制同步電路

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姓名

林沿安(Yan-an Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於800 MHz ~ 1.6 GHz具快速鎖定之全數位脈波寬度控制同步電路
(An 800 MHz ~ 1.6 GHz Fast Locking, All Digital Pulse-Width Control Synchronous Circuit)

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摘要(中)

隨著高速數位電路及記憶體相關電路的操作頻率上升，時脈的扭曲(Skew)愈易造成系統的誤動作。要解決時脈扭曲的問題，時脈同步電路如鎖相迴路(Phase-Locked Loop, PLL)、延遲迴路(Delay-Locked Loop, DLL)及同步複製延遲電路(Synchronous Mirror Delay, SMD)等，便被提出來校正時脈的相位或頻率。而除了同步問題外，時脈扭曲造成的責任週期(Duty cycle)變動，也是需要校正以確保電路操作的可靠度，而脈波寬度控制迴路(Pulse-Width Control Loop, PWCL)便是最常被拿來應用的。在傳統的脈波寬度控制迴路中，向來存在著較大的迴路濾波器面積以及對製程、電壓及溫度(PVT)變異的敏感度問題。在本論文中提出以全數位方法實現的脈波寬度控制電路，除了可克服上述缺點外，由於可程式化的優點，更可提高在系統上應用的可行性。
在本論文中，為了增加輸入訊號的可操作頻率以及可操作責任週期的範圍，使用了脈波產生器和頻率偵測器來自動調校出具適當脈波寬度的時脈，以確保訊號順利於可控延遲線中傳遞。首先在控制機制部分，本論文採用了5位元的時間數位轉換器和4位元的逐漸近似暫存器作為相位控制的粗調以及細調機制。透過控制機制使得複製可控延遲線落後可控延遲線一個週期的時間差，利用多工器選擇兩條延遲線的多相位輸出訊號，則此二個被選擇的訊號間的相位差即可透過SR閂鎖器(SR-latch)轉為輸出訊號的責任週期。最後在訊號輸出前，利用一個簡單的同步複製延遲電路對進入SR閂鎖器前的訊號進行同步的功能，如此便可在訊號輸出時具有與輸入訊號相位同步的功能。
本作的輸出訊號責任週期可控範圍為30 ~ 70%，以每10%作為單位，最高操作頻率為1.6 GHz，在模擬上的抖動為8.8 ps，面積為0.076 mm2。操作在輸入頻率為1.6 GHz 供應電壓為1.2 V時，功率消耗約為26 mW。

摘要(英)

With the raising of operation frequency in system-on-a-chip (SoC), clock skew becomes a more important issue needed to be solved. Phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror delay (SMD) are used to deskew clock skew in phase and frequency. Except phase alignment, duty cycle distortion is needed to calibrate for system reliability. And pulse-width control loop (PWCL) stands to suppress clock skew on duty cycle.
This study proposes a 0.8 ~ 1.6 GHz all-digital synchronous pulse-width control loop in a 90-nm CMOS process. Forsaking the conventional analog PWCL being the enormous filter area cost as well as sensitive to the process, voltage, and temperature (PVT) variations, the all-digital PWCL mitigates such issue, and exhibits the digital implementation for the compact size. By doing so, it is desirable to be used for the relative clock generation to calibrate the clock duty in the SoC and DDR applications.
With regard to the wide operating frequency range and duty cycle of the input clock, the proposed all-digital PWCL uses the pulse generator (PG) and frequency detector (FD) to automatically adjust the appropriate pulse width of the clock, conforming to the successful clock transmission through the variable delay line (VDL) under PVT variations. In addition, based on the 5-bit time-to-digital (TDC) and 4-bit successive approximation register (SAR) architecture for the coarse and fine phase locking, respectively, the output phase of VDL aligns to that of replica VDL (RVDL).Thus, the phase difference between VDL’s and RVDL’s tenth phase output would be the one clock period. Thus, when one of VDL and RVDL stage phases is selected by the following MUX, the phase spacing between two clocks could be similar to the pulse width of the period signal. As a result, through the synchronous mirror delay (SMD) synchronizing the external clock input signal, the SR-latch combines two phase-delayed signals, and the available duty cycle is generated. The proposed all-digital PWCL generates the output clock with the duty cycle of 30 ~ 70 % in steps of 10%. Operating at 1.6 GHz clock rate, the simulated peak-to-peak jitter is 8.8 ps. The chip area occupies 0.076 mm2, and the total power consumption is around 26 mW at supply of 1.2V.

關鍵字(中)

★ 脈波寬度控制電路
★ 同步複製延遲電路
★ 快速鎖定
★ 全數位

關鍵字(英)

★ PWCL
★ SMD
★ Fast Locking
★ All Digital

論文目次

摘要 i
Abstract iii
誌謝 v
目錄 vii
圖目錄 x
表目錄 xiii
第1章緒論 1
1.1 研究動機 1
1.2 研究目的及用途 2
1.3 論文架構 3
第2章相關電路分析 4
2.1 脈波寬度控制迴路 5
2.1.1 傳統的脈波寬度控制迴路(Conventional PWCL) 5
2.1.2 低電壓型的脈波寬度控制迴路(Low-Voltage PWCL) 6
2.1.3 快速鎖定的脈波寬度控制迴路(Fast-Locking PWCL) 7
2.1.4 互補型的脈波寬度控制迴路(Mutual-Correlated PWCL) 8
2.1.5 單路徑型的脈波寬度控制迴路(Single-Path PWCL) 9
2.1.6 高線性度的脈波寬度控制迴路 (High-Linearity PWCL) 10
2.1.7 全數位型的脈波寬度控制迴路(All-Digital PWCL) 11
2.2 相位同步電路 12
2.2.1 閉迴路架構 12
2.2.2 開迴路架構 13
2.3 電路特性比較 14
第3章適用於800 MHz ~ 1.6 GHz具快速鎖定之全數位脈波寬度控制同步電路 16
3.1 設計概念 16
3.2 電路架構及操作 17
3.3 脈波設定部分(Pulse Setting) 18
3.3.1 脈波重塑部分(Pulse Shaping) 19
3.3.1.1 頻率偵測器(Frequency Detector) 19
3.3.1.2 脈波產生器(Pulse Generator) 22
3.3.2 一個週期的時間差產生部分(One Period Spacing Generation) 25
3.3.2.3 可控延遲線及複製可控延遲線(Variable Delay Line & Replica Variable Delay Line) 25
3.3.2.4 邊緣偵測器(Edge Detector) 31
3.3.2.5 時間數位轉換器(Time to Digital Convertor) 34
3.3.2.6 相位偵測器(Phase Detector) 36
3.3.2.7 逐漸近似暫存器(Successive Approximation Register) 39
3.4 相位同步部分 41
3.4.1 SR閂鎖器(SR-Latch) 41
3.4.2 突波產生器(One shot circuit) 43
3.4.3 同步複製延遲電路(Synchronous Mirror Delay) 45
第4章電路模擬及量測考量 46
4.1 設計流程及系統分析 46
4.1.1 設計流程 46
4.1.2 電路動作流程 47
4.1.3 穩定度分析 48
4.1.4 準確度分析 49
4.1.5 電路匹配度 50
4.2 電路模擬 53
4.3 電路佈局及量測考量 59
4.3.1 電路佈局及打線腳位考量 59
4.3.2 輸入訊號考量 62
4.3.3 輸出訊號考量 63
4.3.4 量測環境考量 64
第5章結論 65
5.1 結論 65
5.2 未來改進方向 67
參考文獻 68

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2012-11-30

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