適用於數位家庭之可延展影像壓縮系統之VLSI實現

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姓名

李宗鴻(Zong-hong Li) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於數位家庭之可延展影像壓縮系統之VLSI實現
(VLSI Implementation of Scalable Video Compressor for Digital Home)

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摘要(中)

近年來無線數位家庭系統建制為多媒體發展之趨勢。如果全面採用無線傳輸，則可以避免許多不必要的傳輸線材，使得家庭擺設不受傳輸線材限制。然而，為了讓許多多媒體裝置間能夠互相傳輸，並且能夠打破距離以及移動速度之限制，因此需要建制新的無線多媒體傳輸系統並建制中央控管單元。在系統建制中，多媒體壓縮是相當重要的一環。因為如果多媒體無失真壓縮倍率高，則無線傳輸的頻寬可以相對增加，因為所傳輸的多媒體資料流較小。而且，採用無失真或者近乎無失真傳輸也可以確保傳出的畫質能夠保持在一定程度中。在本篇論文中我們提出一無失真可延伸之圖片/影像壓縮系統，稱之為SS-SIVC，用以建立快速且有效之壓縮系統。
本論文的系統針對無線數位家庭系統條件設計，因此低的複雜度以及壓縮系統有效的設計變成重要關鍵。經由整體的系統考量後，制定出整個系統的演算法流程，並將系統硬體實現與JPEG 2000比較。在比較中可以發現，我們的壓縮倍率在平均上少了0.04，然而整體運算之速度卻快了3倍並且在硬體的使用上減少許多。因此可以證實我們所設計出來的壓縮系統的確比起之前架構有效率許多。本論文所提出硬體編碼器的處理能力可以完全涵蓋 Full-HD 1080p@30Hz。更進一步的，在硬體設計上擁有彈性增加平行度的能力。可利用增加硬體份數的方式來因應更高的顯示規格，如 QHD 及 QFHD。

摘要(英)

Wireless digital home environment is constructed to serve the multiple client and multiple video source requests without the need on wire transmission. To serve these issues, a new video compressor for lossless and near lossless compression is one of the major components achieving wireless mobile, multiple access home entertainment system. In this thesis, a new lossless compression codec, the size and SNR scalable image-video compression codec (SS-SIVC) is proposed.
According to the probability analysis, two-pass quality driven bit plane sequencer is presented. A complete flowchart is constructed to conclude the proposed work. Quality driven magnitude refinement is also proposed to optimize the SNR scalability. According to the experiment results, the computation time of proposed work is almost one third of openJPEG (JEPG 2000) while the compression ratio is only 0.04 behind. According to the results, a computation efficient size and SNR scalable codec is concluded. The proposed work is also implemented in hardware with VLSI architecture. The proposed SS-SIVC codec is fully compatible for Full-HD 1080p@30Hz. Furthermore, with capacity of flexible parallelism, the hardware architecture can be improved for advanced display specifications, such as QHD and QFHD.

關鍵字(中)

★ 無損耗壓縮
★ 可延展性
★ 影像壓縮

關鍵字(英)

★ Lossless compression
★ scalability
★ video compression

論文目次

摘要 I
ABSTRACT II
CHAPTER 1 - 1 -
INTRODUCTION - 1 -
1.1 MOTIVATION - 2 -
1.2 THESIS ORGANIZATION - 4 -
CHAPTER 2 - 5 -
BACKGROUND - 5 -
2.1 VIDEO BASED COMPRESSOR / IMAGE BASED COMPRESSOR - 6 -
2.2 JPEG2000 - 7 -
2.3 DISCRETE WAVELET TRANSFORM (DWT) - 9 -
2.4 MQ-CODER - 10 -
2.5 M-CODER - 11 -
CHAPTER 3 - 13 -
SIZE AND SNR SCALABLE IMAGE-VIDEO COMPRESSION CODEC (SS-SIVC) - 13 -
3.1 DESIGN CONSIDERATION IN SS-SIVC AND BITSTREAM ORGANIZATION - 14 -
3.2 THE FLOWCHART FOR SS-SIVC CODEC AND QUALITY DRIVEN BITPLANE SEQUENCER - 15 -
3.3 EXPERIMENT RESULTS - 17 -
CHAPTER 4 - 19 -
ARCHITECTURE DESIGN OF SS-SIVC - 19 -
4.1 OVERALL HARDWARE SYSTEM DIAGRAM - 20 -
4.2 DESIGN OF LIFTING-BASED DWT - 20 -
4.3 DESIGN OF BIT-PLANE SEQUENCER WITH SS-SIVC ENCODER - 24 -
4.4 DESIGN OF THE PIPELINED M-CODER - 25 -
4.5 DESIGN OF THE PIPELINED MQ-CODER - 33 -
CHAPTER 5 - 36 -
EXPERIMENT RESULTS - 36 -
5.1 DESIGN AND VERIFICATION STRATEGY - 37 -
5.2 CHIP SPECIFICATION - 38 -
5.3 EXTENDED TO MULTI-BLOCK PARALLELISM - 39 -
5.4 IMPLEMENTATION ON SMIMS SOC-150 - 43 -
5.5 HARDWARE PERFORMANCE EVALUATION - 47 -
CHAPTER 6 - 50 -
CONCLUSION - 50 -

參考文獻

[1] “Wireless HD homepage,” Website, January 2008, http://www.wirelesshd.org/.
[2] “WHDI homepage,” Website, http://www.whdi.org/.
[3] JPEG 2000 Part I Final Committee Draft Version 1.0, ISO/IEC Std., March 2000.
[4] “OpenJPEG version 1.4 — an open-source JPEG 2000 codec,” Website, January 2011, http://www.openjpeg.org/.
[5] W. Pearlman, A. Islam, N. Nagaraj, and A. Said, “Efficient, low-complexity image coding with a set-partitioning embedded block coder,” Circuits and Systems for Video Technology, IEEE Transactions on, vol. 14, no. 11, pp. 1219 – 1235, nov. 2004.
[6] A. Said and W. Pearlman, “A new, fast, and efficient image codec based on set partitioning in hierarchical trees,” Circuits and Systems for Video Technology, IEEE Transactions on, vol. 6, no. 3, pp. 243 –250, jun 1996.
[7] S.-T. Hsiang, “Embedded image coding using zeroblocks of subband/wavelet coefficients and context modeling,” in Data Compression Conference, 2001. Proceedings. DCC 2001., 2001, pp. 83 –92.
[8] I. Daubechies and W. Sweldens, “Factoring wavelet transforms into lifting steps,” Journal of Fourier Analysis and Applications, vol. 4, no. 3, pp. 247–269, 1998.
[9] C.-T. Huang, P.-C. Tseng, and L.-G. Chen, “Generic ram-based architectures for two-dimensional discrete wavelet transform with line-based method,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 7, pp. 910 – 920, july 2005.
[10] C.-T. Huang, P.-C. Tseng, and L.-G. Chen,, “Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform,” IEEE Transactions on Signal Processing, vol. 52, no. 4, pp. 1080 – 1089, april 2004.
[11] B.-F. Wu and C.-F. Lin, “A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of jpeg2000 codec,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 12, pp. 1615 – 1628, dec. 2005.
[12] T.-H. Tsai, Y.-H. Lee, and Y.-Y. Lee, “Design and analysis of high-throughput lossless image compression engine using VLSI-oriented FELICS algorithm,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 1, pp. 39 –52, jan. 2010.
[13] W. Sweldens, “The lifting scheme: A new philosophy in biorthogonal wavelet constructions,” in Wavelet Applications in Signal and Image Processing III, pp. 68-79, Proc. SPIE 2569, 1995.
[14] W. B. Pennebaker and J. L. Mitchell, “An overview of the basic principles of the Q-coder adaptive binary arithmetic coder,” IBM J. Res. Develop. Vol. 32, no. 6, November 1988.
[15] W. B. Pennebaker and J. L. Mitchell, “Probability estimation for Q-coder,” IBM J. Res. Develop. Vol. 32, no. 6, November 1988.
[16] M. Dyer, D. Taubman, and S. Nooshabadi, "Improved Throughput Arithmetic Coder for JPEG2000", International Conference on Image Processing, vol.4, pp. 2817-2820, Singapore, 2004.
[17] Y. Li, M. Elgamel, and M. Bayoumi, "A Partial Parallel Algorithm and Architecture for Arithmetic Encoder in JPEG2000", Vol. 5, pp. 5198-5201, ISCAS, Japan, 2005.
[18] G. Pastuszak, "A novel architecture of arithmetic coder in JPEG2000 based on parallel symbolencoding", Inter. Conf. on Parallel Computing in Electrical Engineering, pp. 303-308, Germany, 2004.
[19] M.kuizhi, Z.Nanning, U.Ji, L.Yuehu, "Design of high speed Arithmetic Encoder", 7th International Conference on Solid-State and Integrated-Circuit Technology, vol. 3, pp. 1617-1620, China, 2004.
[20] K.Zhu, F.Wang,X.Zhou, and Q.Zhang, "An efficient accelerating architecture for tier-1 coding in JPEG2000", 7th International Conference on Solid-State and Integrated-Circuit Technology, vol. 3, pp. 1653-1656, China, 2004.
[21] D. Marpe, H. Schwartz and T.Wiegand, “Context-Based Adaptive Binary Arithmetic Coding in the H.264/AVC video compression standard”, IEEE Transaction on Circuits System Video Technology, vol. 13, no. 7, pp. 620–636, July 2003.
[22] K. Mei, N. Zheng, C. Huang, Y. Liu, and Q. Zeng, “Vlsi design of a high-speed and area-efﬁcient jpeg2000 encoder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 8, pp. 1065–1078, aug. 2007.
[23] Y.-H. Seo and D.-W. Kim, “VLSI architecture of line-based lifting wavelet transform for motion jpeg2000,” IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 431 –440, feb. 2007.
[24] T.-T. Lin and J.-S. Chiang, “Low cost architecture for jpeg2000 encoder without code-block memory,” in 2008 IEEE International Conference on Multimedia and Expo, apr. 2008, pp. 137 –140.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2012-12-7

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