適用於二元脈衝振幅調變系統之高速共時適應性決策回授等化器

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林育羣(Yu-Chun Lin) 查詢紙本館藏

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電機工程學系

論文名稱

適用於二元脈衝振幅調變系統之高速共時適應性決策回授等化器
(High Throughput Concurrent Adaptive Decision Feedback Equalizer for 2-PAM Systems)

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摘要(中)

適應性決策回授等化器(ADFE)從效能與硬體複雜度考量皆優於線性等化器，因此被廣泛的使用於通信傳輸系統中，用來消除通道所造成之符號間彼此干擾現象。然而，因為適應性決策回授等化器在係數修正與資料等化處理上皆有回授路徑，會影響到實際所能處理的資料速度，導致適應性決策回授等化器在高速應用上受到一定的限制。理論上，要打破回授的限制必須要在回授路徑上做前瞻運算，接著利用平行化來達到增加速度的目的。傳統上會採用資料前瞻的做法，然而資料前瞻必須先將所有可能結果算出，導致硬體複雜度隨著平行化與等化器係數長度而快速增加。
有別於傳統作法，本論文於二元脈衝振幅調變系統中之接收端等化器提出係數前瞻法，也就是利用算出回授等化器的前瞻係數而達到打斷回授路徑的目的。此外，配合該係數前瞻演算法，我們也提出自我前瞻濾波器架構以降低整體運算複雜度。該架構除了在訊雜比 (SNR)上具有與傳統非平行適應性決策回授等化器有相近的表現之外，面積上還具有比其他已知的平行適應性決策回授等化器擁有小非常多的優點。在係數修正方面，我們提出一套降速修正的演算法(Batch Mode Coefficients Update, BMCU)，該演算法可以兼顧追蹤通道變化以及達到高速等化資料的需求。此外，為了避免雜訊被前饋濾波器 (FFF) 放大，本論文提出前饋濾波器雜訊抑制型適應性決策回授等化器的架構 (FNS-ADFE)。模擬結果顯示，相比於傳統ADFE，FNS-ADFE可提升2 dB 訊雜比或降低錯誤率到百分之一。
實作上是採用40 nm CMOS-GP製程。該測試晶片的面積為275 μm × 275 μm (或約等效於28.5 k 個邏輯閘)。平均功率消耗在低供應電壓低資料率時（0.75V, 10 Gbps）為 2.3 pJ/bit、在正常供應電壓中資料率時（0.9V, 13 Gbps）為3.5 pJ/bit、而在高供應電壓高資料率時（1.1V, 16 Gbps）為 5.8 pJ/bit。

摘要(英)

Adaptive Decision Feedback Equalizers (ADFEs) are widely used to reduce the inter-symbol interferences (ISIs) caused by channels in communication systems since ADFEs are better than Adaptive Linear Equalizers (ALEs) in both signal-to-noise ratio (SNR) and hardware complexity points of views. However, the data rate of an ADFE is limited due to the feedback path in both the coefficients update part and the data equalization part. In theorem, to do lookahead and then parallel can eliminate the limitation of data rate and the data lookahead scheme is usually used. Data lookahead scheme requires calculating all-possible results; hence the hardware complexity grows quickly with the parallelism and the tap-number of the ADFE.
In this dissertation, we propose the coefficients-lookahead scheme for the ADFEs in the receivers of 2-level Pulse Amplitude Modulation (2-PAM) systems, that is, to find out the coefficients for lookahead scheme. Based on the coefficients-lookahead scheme, the self-lookahead filter and the high speed architecture are proposed. The proposed architecture has almost the same SNR with conventional ADFE and has hardware complexity growing slowly with parallelism. In coefficients adaption, we propose a slow updating method, Batch Mode Coefficients Update (BMCU) algorithm to fit the requirement for channel tracking and high data rate. Besides, to avoid noise enhancement at the feed-forward filter (FFF), a FFF noise-suppression ADFE (FNS-ADFE) architecture is proposed which has 2 dB better SNR or 1% less bit error rate than that of a conventional ADFE.
The test-chip has been fabricated in a 40nm CMOS-GP technology with the core size as 275 μm × 275 μm (or 28.5k equivalent gates count), and dissipates 2.3 pJ/ bit at 10 Gbps with low-supply voltage (0.75 V), 3.5 pJ/bit at 13 Gbps with normal-supply voltage (0.9 V) and 5.8 pJ/bit at 16 Gbps with high-supply voltage (1.2 V).

關鍵字(中)

★ 等化器
★ 決策回授
★ 前瞻演算法
★ 數位
★ 高速
★ 適應性

關鍵字(英)

★ Equalizer
★ DFE
★ Lookahead
★ Digital
★ High Speed
★ Adaptive

論文目次

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Applications 4
1.3.1 Multi-Mode Fiber (MMF) 4
1.3.2 Universal Serial Bus (USB) 5
1.4 Organization 5
Chapter 2 Overview of High Throughput Adaptive Decision Feedback Equalizers 7
2.1 Channel Model 8
2.2 Linear Equalizer vs. Decision Feedback Equalizer 10
2.2.1 Linear Equalizers 11
2.2.2 Decision Feedback Equalizers 14
2.3 Adaptive Algorithms 17
2.3.1 Steepest Descent 17
2.3.2 Least Mean Square (LMS) 20
2.3.3 Delayed Least Mean Square Error (DLMS) 22
2.3.4 Sign-Sign Least Mean Square Error (SS-LMS) 23
2.3.5 Blind Least Mean Square (Blind LMS) Algorithm for Adaptive Decision Feedback Equalizer 24
2.4 Data Throughput Rate Limitation 26
2.5 High Throughput Architectures for Adaptive Decision Feedback Equalizer 30
2.5.1 Relaxed Look-Ahead (RLA) 31
2.5.2 Two-Stages Pre-computation (TSP) 34
2.5.3 Batch-time Parallelization (BP) 35
2.5.4 Real-time Parallelization (RP) 37
2.6 Summary 38
Chapter 3 Proposed Real-time Parallelization Architecture for Adaptive Decision Feedback Equalizers 39
3.1 Channel Model 40
3.2 Batch Mode Coefficients Update (BMCU) Unit 41
3.3 Lookahead Schemes for Parallel Adaptive Decision Feedback Equalizers 47
3.3.1 Lookahead Concept 47
3.3.2 Incremental Lookahead 49
3.3.3 Incremental Data Lookahead Adaptive Decision Feedback Equalizer (IDL-ADFE) 51
3.4 Proposed Incremental Coefficient-Lookahead Adaptive Decision Feedback Equalizer (ICL-ADFE) 55
3.4.1 Paralleled Multiple Input Feedforward Filter (PMI-FFF) 56
3.4.2 Paralleled Multiple Input Feedback Filter (PMI-FBFL) 57
3.4.3 Hardware Complexity 62
3.4.4 Simulation Results 64
3.5 Proposed Extended Incremental Coefficient-Lookahead Adaptive Decision Feedback Equalizer (EICL-ADFE) 67
3.5.1 Self-Lookahead Filters 68
3.5.2 Extended Filters 70
3.5.3 Hardware Complexity 74
3.5.4 Simulation Results 75
3.6 Summary 77
Chapter 4 Feedforward-Filter Noise Suppression Adaptive Decision Feedback Equalizer (FNS-ADFE) 78
4.1 Noise Enhancement Effect of A Conventional Decision Feedback Equalizer 79
4.2 AWGN Noise Free Decision Feedback Equalizer 81
4.3 Feedforward-Filter Noise Suppression Adaptive Decision Feedback Equalizer (FNS-ADFE) 84
4.4 Error Propagation Analysis 86
4.4.1 Possible States and State Probability Vector 86
4.4.2 State Transformation Matrix V 89
4.5 Simulation Results 93
4.6 Summary 95
Chapter 5 Hardware Implementation of Extended Incremental Coefficient-Lookahead Adaptive Decision Feedback Equalizer 96
5.1 Self Test Circuit 98
5.1.1 Pseudo Random Binary Sequence 98
5.1.2 Build-in Channel 99
5.1.3 Comparison Unit 100
5.2 Architecture of the Proposed Design 101
5.2.1 Batch Mode Coefficients Update (BMCU) 101
5.2.2 Feed-Forward Filters (FFFs) 106
5.2.3 Extended Filters (EFs) 107
5.2.4 Self-Lookahead Filters (SLFs) 108
5.3 Simulation Results 109
5.4 Implementation Results 113
5.5 Summary 117
Chapter 6 Conclusion and Future Work 118
Bibliography 120

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指導教授

周世傑、薛木添
(Shyh-Jye Jou、Muh-Tian Shiue)

審核日期

2013-1-29

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