應用於K / V 頻段低功耗混頻器之研製

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姓名

郭士慶(Shih-Ching Kuo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於K / V 頻段低功耗混頻器之研製
(Implementation on Low Power Mixers for K and V band Applications)

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摘要(中)

本論文主要研究K / V 頻段的低功耗混頻器，共實做出三個混頻器晶片。論文主要分為兩個部分，第一部分為使用電流注入與電流再利用技術之K頻段低功耗雙平衡混頻器實做於tsmc 0.18-μm CMOS製程，利用電流再生技術達到低功耗的效果，並使用電流注入技術提高轉換增益。量測的結果顯示，當本地振盪功率為1 dBm時有最大的轉換增益0.8 dB，輸入功率1-dB壓縮點為-8 dBm，三階交互調變失真點為6 dBm，3-dB頻寬為16-30 GHz，總功率消耗為9.9 mW，電路面積為0.71 mm2。
第二部分為使用被動結合器之閘極驅動混頻器架構，使用此架構取代吉伯特混頻器可降低供給電壓和功耗，並偏壓在弱反轉層可進一步的降低整體功耗，第二部分第一顆晶片為使用被動結合器之V頻段低功耗雙平衡閘極驅動混頻器實做於tsmc 90-nm CMOS製程，利用被動結合器將差動射頻訊號和差動本地振盪訊號相加，將相加訊號輸入電晶體閘級，利用閘極驅動的方式來混頻，且使用雙平衡架構可得到較高的隔離度，並使用逆變緩衝器提高轉換增益。量測的結果顯示，當本地振盪功率為0 dBm時有最大的轉換增益2.3 dB，輸入功率1-dB壓縮點為10 dBm，三階交互調變失真點為2 dBm，3-dB頻寬為60-66 GHz，總功率消耗為4.3 mW，電路面積為0.61 mm2。
第二部分第二顆晶片為使用變壓結合器之K頻段次諧波低功耗單平衡閘極驅動混頻器實做於tsmc 0.18-μm CMOS製程，利用變壓結合器產生寬頻的射頻頻寬和將差動射頻訊號和差動本地振盪訊號相加，將相加訊號輸入電晶體閘級，利用閘極驅動的方式來混頻，並加入兩段四分之一波長的傳輸線來改善射頻到中頻和兩倍本地震盪到中頻的隔離度。量測的結果顯示，當本地振盪功率為1 dBm時有最大的轉換增益1 dB，輸入功率1-dB壓縮點為8 dBm，三階交互調變失真點為3 dBm，3-dB頻寬為14-30 GHz，總功率消耗為7.8 mW，電路面積為0.63 mm2。

摘要(英)

This thesis researches on low power mixers for K and V band applications, and achieved a total of three mixer chips. Two kinds of mixers are studied. The first one is a K band low power double-balanced mixer using current reused and current bleeding techniques that is implemented in tsmc 0.18-μm CMOS process. This design adopted current reused technique to reduce power consumption and using current bleeding technique to enhance conversion gain. The measured results show that the maximum conversion gain of -0.8 dB, an input 1-dB compression point of - 8 dBm and input third order intercept point of 6 dBm. The obtained 3-dB bandwidth is from 16-30 GHz at 1-dBm LO driving power. The total power consumption including the output buffer is 9.9 mW. The chip size is 0.63 mm2.
Two gate-pumped mixers with passive combiners are proposed. Compared with Gilbert cell mixer, the gate-pumped mixers with passive combiners can reduce supply voltage and lower power consumption. By using weak inversion biasing can further reduce total power consumption.
The first gate-pumped mixer is a V-band low power double balanced gate-pumped mixer using passive combiner in tsmc 90-nm CMOS process. A passive combiner is used to combine differential RF and LO signals. The combined signals are injected into each gate of the transistors of mixed stage, and utilizing gate pumped topology to yield the frequency conversion. While using double balanced toplogy to improve port-to-port isolation, and inverter buffers are adopted to increase the conversion gain. The measured results show that the maximum conversion gain of -2.3 dB, an input 1-dB compression point of -10 dBm and input third order intercept point of 2 dBm. The 3-dB bandwidth is from 60-66 GHz while the LO driving power of 0 dBm. The total power consumption including the output buffer is 4.3 mW. The chip size is 0.61 mm2.
The second gate-pumped mixer is a K-band sub-harmonic low power single balanced gate-pumped mixer using transformer combiner in tsmc 0.18-μm CMOS process. A transformer combiner is used to produce wide bandwidth of RF frequency and combine differential RF and LO signals. The combined signals are fed into each gate of the transistors of mixed stage, and utilizing gate pumped topology to yield the frequency conversion. Two quarter wavelength transmission lines were adopted to improve the RF-to-IF and 2LO-to-IF isolations. The measured results show that the maximum conversion gain of -1 dB, an input 1-dB compression point of -8 dBm and input third order intercept point of 3 dBm. The 3-dB bandwidth is from 14-30 GHz while the LO driving power of 1 dBm. The total power consumption including the output buffer is 7.8 mW. The chip size is 0.63 mm2.

關鍵字(中)

★ K頻段
★ V 頻段
★ 混頻器
★ 低功耗

關鍵字(英)

★ K band
★ V band
★ mixer
★ low power

論文目次

摘要 V
Abstract VI
誌謝 VIII
目錄 IX
圖目錄 X
表目錄 XII
第一章緒論 1
1-1 研究動機 1
1-2 章節簡述 1
第二章混頻器介紹 2
2-1 混頻器原理 2
2-2 混頻器重要參數介紹 3
2-3 基本混頻器架構介紹 5
第三章使用電流注入與電流再利用技術之K頻段低功耗雙平衡混頻器 10
3-1 前言 10
3-2 電路架構與原理 10
3-3 模擬與量測結果 11
3-4 結果與討論 18
第四章使用被動結合器之V頻段低功耗雙平衡閘極驅動混頻器 19
4-1 前言 19
4-2 電路架構與原理 19
4-3 模擬與量測結果 25
4-4 結果與討論 33
第五章使用變壓結合器之K頻段次諧波低功耗單平衡閘極驅動混頻器 34
5-1 前言 34
5-2 電路架構與原理 34
5-3 模擬與量測結果 41
5-4 結果與討論 50
第六章結論 51
6-1 結論 51
6-2 未來期許和研究方向 52
參考文獻 53

參考文獻

[1] 連婉茹,“V頻段微型化混頻器之研製,” 國立中央大學, 碩士論文, 2006。
[2] H. K. Chiou, K. C. Lin, W. H. Chen, and Y. Z. Juang, “A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver,” IEEE Trans. Circuits Sys. I, vol. 59, no. 6, pp. 1215-1227, Jun. 2012.
[3] S. He and C. E. Saavedra, “An Ultra-low-voltage and low-power ×2 subharmonic Downconverter Mixer,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 2, pp. 311–317, Feb. 2012.
[4] R. Kodkani and L. Larson, “24-GHz CMOS passive subharmonic mixer/downconverter for Zero-IF Applications,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp. 1247–1255, May 2008.
[5] J. H. Tsai and C. C. Wang, “A 25-55 GHz CMOS sub-harmonic direct-conversion mixer for BPSK demodulator,” in Asia–Pacific Microw. Conf., Dec. 2008.
[6] C. C. Wei, H. C. Chiu, H. C. Hsu, W. S. Feng, and J. S. Fu, “Fully integrated 24 GHz differential active sub-harmonic mixer located in CMOS multi-layer Marchand baluns,” IET Microw. Antennas Propag., Vol. 4, Iss. 11, pp. 1789–1798, Nov. 2010.
[7] 梁嘉仁,“應用fT倍頻電路與被動結合器技術於低功率消耗毫米波混頻器之研究,” 國立中央大學, 碩士論文, 2011。
[8] H. T. Chou, J. R. Liang, and H. K. Chiou, “V-band low-power Darlington-pair gate-pumped mixer with thin-film LC-hybrid linear combiner in 90 nm CMOS,” Electronics Lett., vol. 48, no. 16, pp. 1023–1024, Aug. 2012.
[9] Y. Jin, J. R. Long, and M. Spirito, “A 7 dB NF 60 GHz-band millimeter-wave transconductance mixer,” in IEEE Radio Freq. Integr. Circuits (RFIC) Symp., Jun. 2011.
[10] H. K. Chiou and T. Y. Yang, “Low-loss and broadband asymmetric broadside-coupled balun for mixer design in 0.18-μm CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 4, pp. 835–848, Apr. 2008.
[11] J. H. Tsai, “Design of 1.2 V broadband, high data-rate MMW CMOS I/Q modulator and demodulator using modified Gilbert-cell mixer,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1350–1360, May 2011.
[12] J. H. Tsai, “Design of 40–108-GHz low-power and high-speed CMOS up-/down-conversion ring mixers for multistandard MMW radio applications,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 670–678, Mar. 2012.
[13] W. T. Li, H. Y. Yang, Y. C. Chiang, J. H. Tsai, M. H. Wu, and T. W. Huang, “A 453-μW 53–70-GHz ultra-low-power double-balanced source-driven mixer using 90-nm CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 5, pp. 1903–1912, May 2013.
[14] C. H. Lien, P. C. Huang, K. Y. Kao, K. Y. Lin, and H. Wang, “60 GHz double-balanced gate-pumped down-conversion mixers with a combined hybrid on 130-nm CMOS processes,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 3, pp. 160–162, Mar. 2010.
[15] J. R. Long, “A low-voltage 5.1–5.8-GHz image-reject downconverter RF IC,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1320–1328, Sep. 2000.
[16] H. J. Wei, C. C. Meng, T. W. Wang, T. L. Lo, and C. L. Wang, “60-GHz dual-conversion down-/up-converters using schottky diode in 0.18-μm foundry CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 6, pp. 1684–1698, Jun. 2012.
[17] H. K. Chiou and J. Y. Lin, “Symmetric offset stack balun in standard 0.13-μm CMOS technology for three broadband and low-loss balanced passive mixer design,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 6, pp. 1529–1538, Jun. 2011.
[18] H. J. Wei, C. C. Meng, P. Y. Wu, and K. C. Tsung, “K-band CMOS subharmonic resistive mixer with a miniature marchand balun on lossy silicon substrate,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 1, pp. 40–42, Jan. 2008.
[19] J. H. Tsai and T. W. Huang, “35–65 GHz CMOS broadband modulator and demodulator with sub-harmonic pumping for MMW wireless gigabit applications,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 10, pp. 2075–2085, Oct. 2007.
[20] H. K. Chiou and H. T. Chou, “A 0.4 V microwatt power consumption current-reused up-conversion mixer,” IEEE Microw. Wireless Compon. Lett., vol. 23, no. 1, pp. 40–42, Jan. 2013.

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2013-8-13

推文