操作在0.5伏特下具溫度補償技術非石英振盪器之全數位式時脈產生器

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姓名

張啟揚(Chi-Yang Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

操作在0.5伏特下具溫度補償技術非石英振盪器之全數位式時脈產生器
(A 0.5 V All Digital Crystal-less Clock Generator with Temperature Compensation)

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摘要(中)

本論文提出一操作在0.5伏特，具溫度補償機制之非石英式時脈產生器。此架構利用溫度補償電路，針對晶片溫度改變時，將調整時脈產生器之操作頻率，校正到系統所需之操作頻率。當溫度改變時，溫度補償電路利用環形振盪器輸出頻率變化。將其輸出頻率經過時間轉數位轉換器作運算，並送入數位濾波器中，對數位控制振盪器做頻率補償。若校正頻率的幅度不足時，可以調整時間放大器的增益值，將溫度補償電路的修正幅度提高。
本論文之全數位式非石英式時脈產生器使用TSMC 65 nm 1P9M CMOS製程實現晶片，當溫度變化從0°C到100°C時，此全數位非石英式時脈產生晶片之操作頻率可達到300 MHz且操作電壓為0.5 V。其架構實現於65 nm CMOS製程下，電路面積為422×353 um2。其功率消耗為1.05 mW且操作頻率精準度達到±2%。因此，全數位非石英式時脈產生器架構將容易整合於低電壓之操作與數位系統之應用。

摘要(英)

A low voltage all digital crystal-less clock generator (CLCG) is presented. All digital CLCG adopts the temperature compensation circuit to calibrate the CLCG operational frequency. The temperature compensation circuit adjusts the operational frequency of CLCG to achieve the target frequency. The temperature compensation adopts ring oscillator to detect the temperature variations. When the temperature varies, the temperature compensation circuit creates the compensation code and feeds the digital code to digital loop filter (DLF). The DLF output codes can adjust the digital control oscillator (DCO) output frequency. If the target frequency is not arrived, The timing amplifier (TA) gain can be adjusted for frequency compensation.
The experimental chip was fabricated by TSMC 65 nm 1P9M CMOS process. Under the temperature is from 0°C to 100°C, the all-digital CLCG output produces a target frequency of 300 MHz under the 0.5 V supply voltage. The core area is 422×353 um2 in a 65 nm CMOS process. The power consumption and frequency accuracy of CLCG are less than 1.05 mW and ±2%, respectively. This all digital CLCG is suitable for low supply voltage applications and digital systems.

關鍵字(中)

★ 無石英振盪器
★ 溫度
★ 時間放大器
★ 多相位
★ 數位濾波器
★ 補償

關鍵字(英)

★ Crystalless
★ Temperature
★ Timing Amplifier
★ Multi-Phase
★ Digital Loop Filter
★ Compensation

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第1章緒論 1
1.1 研究動機 1
1.2 研究目的及其應用 2
1.3 論文架構 3
第2章非石英式全數位時脈產生器技術探討 4
2.1 非石英式時脈產生器種類簡介 4
2.2 非石英式時脈產生器架構探討 6
2.2.1 溫度補償之弛張振盪器[10] 6
2.2.2 含溫度補償之非石英振盪器[11] 7
2.2.3 具LC振盪器之非石英振盪器[12] 9
2.2.4 應用於生醫系統具頻率追鎖迴路之非石英振盪器[13] 10
2.2.5 非石英式時脈產生器架構規格比較 11
2.3 本論文預計規格 12
第3章具溫度補償機制之非石英式全數位時脈產生器 14
3.1 設計概念 14
3.2 非石英式全數位振盪器架構及操作 16
3.3 初始頻率設定 (Frequency Setting) 18
3.4 溫度漂移(Temperature Variation) 20
3.5 頻率補償(Frequency Compensation) 21
第4章非石英式全數位時脈產生器架構分析與子電路介紹 25
4.1 多重相位數位控制振盪器 (MP-DCO) 25
4.1.1 多重相位數位控制振盪器公式探討[14] 25
4.1.2 多重相位數位控制振盪器架構[15] 28
4.1.3 多重相位數位控制振盪器模擬結果 31
4.2 時間數位轉換器(TDC) 33
4.2.1 時間數位轉換器架構 33
4.2.2 時間數位轉換器模擬結果 36
4.2.3 時間數位轉換器之位元數探討 39
4.3 時間放大器(TA) 40
4.4 非石英式全數位時脈產生器之S-domain分析 41
4.5 數位迴路濾波器[19] 42
4.5.1 計算數位迴路濾波器之參數 43
第5章無石英式時脈產生電路模擬與晶片量測結果 47
5.1 設計流程 47
5.2 電路模擬 47
5.3 電路佈局 50
5.4 晶片照相與量測環境設定 51
5.5 量測結果 53
5.6 規格比較 59
第6章結論與未來研究方向 61
6.1 結論 61
6.2 未來研究方向 62
參考文獻 63

參考文獻

[1] T. Sakurai, “Low power digital circuit design,” IEEE European Solid-State Circuits Conference, pp. 11-18, Sep. 2004.
[2] F. S. L. J. Breems, K. A. A. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, “A low-voltage mobility-based frequency reference for crystal-less ULP radios,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2002–2009, July. 2009.
[3] M. S. McCorquodale, J. D. O’Day, S. M. Pernia, G. A. Carichner, S. Kubba, R. B. Brown, "A monolithic and self-referenced RF LC clock generator compliant with USB 2.0," IEEE J. Solid-State Circuits, vol. 42, pp. 385-399, Feb 2007.
[4] V. D. Smedt, P. D. Wit, W. Vereecken, and M. S. J. Steyaert, “A 66 uW 86 ppm/°C fully-Integrated 6 MHz wienbridge oscillator with a 172 dB phase noise FOM,” IEEE J. Solid-state Circuits, vol.44, no. 7, pp. 1990-2001, Jul. 2009.
[5] J. Lee and S. Cho, “A 10MHz 80μW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS,” in Proc. IEEE Symp. on VLSI, 2009, pp. 226–227.
[6] S. L. J. Gierkink and Ed (A. J. M.) v. Tuijl, “A coupled sawtooth oscillator combining low jitter with high control linearity,” IEEE J. Solid-state Circuits, vol.37, no. 6, pp. 702-710, Jun. 2002.
[7] J.-C. Liu, W.-C. Lee, H.-Y. Huang, K.-H. Cheng, C.-J. Huang, Y.-W. Liang, J.-H. Peng, and Y.-H. Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in proc. Asian Solid-State Circuits Conference, 2012, pp.117-120.
[8] U. Denier, “Analysis and design of an ultralow-power CMOS relaxation oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, Aug. 2010.
[9] Y.-C. Shih and B. Otis, “An on-chip tunable frequency generator for crystal-less low-power WBAN radio,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 60, no. 4, Apr. 2013.
[10] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, "An on-chip CMOS relaxation oscillator with voltage averaging feedback", IEEE J. Solid-State Circuits, vol. 45, no. 6, pp.1150 -1158, 2010.
[11] F. Sebastiano , L. Breems , K. Makinwat , S. Drago , D. Leenaerts and B. Nauta, ”A 65-nm CMOS temperature-compensated mobility-based fre- quency reference for wireless sensor networks,” IEEE J. Solid-State Circuits, vol. 45, no. 7, pp. 1544–1552, July. 2011.
[12] M. S. McCorquodale, S. M. Pernia, J. D. O’Day, G. Carichner, E. Marsman, N. Nguyen, S. Kubba, S. Nguyen, J. Kuhn, and R. B. Brown, “A 0.5-to- 480MHz self-referenced CMOS clock generator with 90ppm total frequency error and spread-spectrum capability,” in IEEE ISSCC Dig. Tech. Papers, pp. 350-351, 2008.
[13] W.-H. Sung, S.-Y. Hsu, J.-Y. Yu, C.-Y. Yu, and C.-Y. Lee, “A frequency accuracy enhanced sub-10uW on-chip clock generator for energy Efficient crystal-less wireless biotelemetry applications,” in Proc. IEEE Symp. on VLSI, 2010, pp. 115–116.
[14] H.-Y. Huang, and F.-C. Tsai, ‘‘Analysis and optimization of ring oscillator using sub-feedback scheme,’’ in Proc. IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems, Apr. 2009, pp. 28-29.
[15] Yong-Jhen Jhu,2011,‘‘A 4-GHz 10-Phase all digital phase-locked loop’’， NCU M. Thesis, Oct. 2011.
[16] P. Dudek, S. Szczepanski, and J. Hatfield, ” A high-resolution CMOS time -to-digital converter utilizing a vernier delay line,” IEEE J. Solid-state Circuits, vol.35, pp. 240-247, Feb. 2000.
[17] A. H. Chan, and G.W. Roberts “A deep sub-micron timing measurement circuit using a single-stage vernier delay line,” IEEE Proc. CICC, pp. 77-80, May 2002.
[18] H.-Y. Huang, W.-C. Hung, H.-W. Cheng, and C.-H. Lu, “All digital time-to-digital converter with high resolution and wide detect range,” Engineering Letters, Aug. 2011.
[19] V. Kratyuk, ‘‘Digital phase-locked loops for multi-GHz clock generation,” OSU Ph. D. Thesis, Dec. 2006.
[20] M. Kashmiri, M. Pertijs, and K. Makinwa, “A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C,” IEEE J. Solid-state Circuits, vol.45, pp.2510-2520, Dec 2010.
[21] K.-H. Cheng, C.-C. Hu, J.-C. Liu, and H.-Y. Huang, “A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop,” in Proc. IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems, Apr. 2010, pp. 285-288
[22] W.-H. Sung, J.-Y. Yu, and C.-Y. Lee, “A robust frequency tracking loop for energy-efficient crystal-less WBAN system,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 58, no. 10, Oct. 2011.
[23] K. Sundaresan, P. E. Allen, and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-state Circuits, vol.41, no. 2, pp. 433-442, Feb. 2006.
[24] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, “An on-chip CMOS relaxation oscillator with power,” in IEEE ISSCC Dig. Tech. Papers, pp. 404-405, 2009.
[25] P. F. J. Geraedts, E. v. Tuijl, E. A. M. Klumperink, G. J. M. Wienk, and B. Nauta, “A 90µW 12MHz relaxation oscillator with a -162dB FOM,” in IEEE ISSCC Dig. Tech. Papers, pp. 348-349, 2008.
[26] K. Choe, O. D. Bernal, D. Nuttman2, and M. Je, “A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 402–403.
[27] M. Kashmiri, M. Pertijs, and K. Makinwa “A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C,” in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 74–75.
[28] Y. Lu, G. Yuan, L. Der, W.-H. Ki, and C. P. Yue, “A ±0.5% precision on-chip frequency reference with programmable switch array for crystal-less applications” IEEE Trans. Circuits Syst. II, Exp. Briefs, to be published.
[29] L. Zhou, M. Annamalai, J. Koh, M. Je, L. Yao, and C.-H. Heng,”A crystal- less temperature-independent reconﬁgurable transmitter targeted for high-temperature wireless acoustic telemetry applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 9, Sep. 2013.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2013-10-8

推文