用於二維電阻串聯陣列之通道棍型繞線法

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姓名

張宇翔(Yu-hsiang Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於二維電阻串聯陣列之通道棍型繞線法
(Channel Sticks Routing for a Resistor-string Array)

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摘要(中)

半導體製程的技術隨著時代的演進，使的元件尺寸微縮、彼此間距離逐漸接近，因製程變動(process variation)引發的元件不匹配與導線寄生效應的變動也隨之劇烈，此外，類比電路在設計上複雜度的提高也使其成為整體混合訊號電路設計的瓶頸，故其是否能有可靠的自動化實現將會成為提升整體電路設計之效率的關鍵點。
電阻串聯式數位/類比轉換器電路中，串聯電阻陣列用以提供轉換電路連續參考偏壓，藉由電阻串陣列的排列與其元件間的空間相關性提昇電阻本身在抑制製程變異的能力，可以有效的降低電路的隨機誤差(random error)，然而，電阻串聯式數位/類比轉換器的高精確度及電阻串陣列本身的排列擺置，皆會提高其在實體佈局、繞線上的困難度，導線寄生阻值的不一致性將會引起電路的系統誤差(systematic error)，增加積分非線性誤差，在這樣的考量下，一個好的排列，若未能在實體佈局層面上自動化實現與寄生效應平衡，其終將功虧一簣，故自動化繞線與連接線(interconnect)阻值平衡已然不可或缺。
本論文中，針對這樣的問題，首先定義串聯電阻陣列繞線問題的矩陣模型，在此模型的基礎上，我們可以確保每一條電阻間的導線均具有相同的水平、垂直金屬層分配(IC-level channel routing)、相同的VIA區塊、一致的電阻連接形式，接著我們提出一個電阻串陣列通道棍型繞線法，應用於任意排列、任意位元數之電阻串的自動化佈局、繞線上，將其實現在極度不規則的探戈行軍式蛇行、螺旋電阻陣列排法中，並平衡不同導線長度下的寄生電阻值，同時開發一個圖型使用者介面(GUI)工具，提供使用者做繞線資訊的設定

摘要(英)

As the evolution of the semiconductor process technology, the process variation will be more and more serious in device mismatch and wire parasitic. In addition, analog circuit design process can easily become the bottleneck in the overall SoC design process, mainly because it is much more complicated and error-prone. A reliable automation tool will become the key point to enhance the efficiency of the overall circuit design.
For the series resistor array in resistor-string DAC, we can effectively reduce the random error by the permutation and space correlation of resistors. However, the high precision resistor string and resistor array permutation will increase the difficulty of the physical layout, and the inconsistency of the parasitic resistance will cause the circuit system error. In this consideration, if a good arrangement can not be achieved in the physical layout automation and balance parasitic effects, it will eventually fall short. So the automated routing and interconnect resistance balance has already indispensable.
In this thesis, first, we define the matrix model of the series resistor array routing problem. On the basis of this model, we can ensure that each resistor connected wires having the same layer distribution, the same number of VIA block, and the consistent connection form. Then we propose a channel sticks routing for a resistor-string array, which applied to arbitrary permutation, any bits resistor strings automation layout and routing. Furthermore, this method will achieve in extremely irregular Tango march permutation, and balance the drastic interconnect resistance variation. While developing a graphical user interface (GUI) tool, it can provide users to set routing information, and present the parasitic resistance analysis of each wire in the overall routing clearly.

關鍵字(中)

★ 電阻串陣列
★ 通道繞線
★ 導線匹配
★ 自動化

關鍵字(英)

★ resistor-string Array
★ channel routing
★ interconnect match
★ automate
★ TCK/TK

論文目次

中文摘要.....................................................................................................i
Abstract......................................................................................................ii
誌謝...........................................................................................................iv
目錄............................................................................................................v
圖目錄......................................................................................................vii
表目錄.......................................................................................................ix
第一章緒論……………..……….…………………………………...…1
1.1 動機與背景……..…………………………………………………………....1
1.2 論文組織……………………………………………………………………..3
第二章預備知識……………………………………………………….4
2.1 電阻的實體佈局基本概念…………………………………………………..4
2.2 Tango行軍式電阻串…………………………….………………………….7
2.2.1 一維Tango式擺放……………………………………………….……8
2.2.2　二維Tango行軍式排列……………………………………………….9
2.3 數位/類比轉換器靜態特性參數定義……………………………………….9
2.3.1 電阻串聯式數位/類比轉換器架構簡介………………………………10
2.3.2 單調性….…………………………………………………………..…..12
2.3.3 最佳迴歸線……...……………………………………………………..12
2.3.4 LSB Step Size…..…………………………………………………….13
2.3.5 微分非線性誤差…...…………………………………………………..14
2.3.6 積分非線性誤差…….…………………………………………………14
2.4 導線連接一致性…………………….………………..…………………….15
2.4.1 路徑與金屬層考量…………………….………………………………16
2.4.2 三段水平兩段垂直走線….………………………………………..…..17
第三章演算法………………………………………………..………..20
3.1 通道棍型繞線問題描述.................................................................................20
3.1.1 串聯電阻陣列之平衡寄生阻值自動化繞線..........................................22
3.1.2 矩陣模型定義..........................................................................................22
3.2 導線寄生阻值平衡機制................................................................................27
3.3 通道棍型繞線................................................................................................29
3.4 演算法架構……………................................................................................30
第四章實驗結果與分析........................................................................33
4.1 Laker軟體與TCL/TK....................................................................................33
4.2 實現結果........................................................................................................33
4.2.1 圖型使用者介面.....................................................................................34
4.2.2 自動化繞線結果與導線寄生阻值比較……………………………….36
第五章結論............................................................................................41
參考文獻..................................................................................................43

參考文獻

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http://en.wikipedia.org/wiki/Electrical_resistivity_and_conductivity
【4】 Passive components in CMOS Technology
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【16】 Wikipedia. Tcl [Online]. Available: http://en.wikipedia.org/wiki/Tcl

指導教授

陳竹一(Jwu-E Chen)

審核日期

2013-11-28

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