具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路

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姓名

李柏逸(Po-Yi Li) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路
(A Fast-locking Phase-locked Loop with a Digital Band Selector and an Adaptive Phase Frequency Detector)

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摘要(中)

本論文實現了一個快速鎖定的鎖相迴路，在不使用電感的狀況下，使用四級雙端延
遲元件組成之震盪器能提供八個相位震盪頻率為5 GHz的輸出訊號。整體電路架構採用了多頻帶的電壓控制震盪器來降低KVCO，並利用頻帶選擇器決定出合適的頻帶。為了加速頻帶上的追鎖過程則使用了可適性相位頻率偵測器，使控制電壓能較為迅捷地改變，藉此快速消弭相位差，達到快速鎖定的效果。
本論文實現之具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路使
用TSMC 90 nm(TN90GUTM) 1P9M 製程來實現，電路操作電壓為1 V。鎖相迴路的輸入參考時脈為50 MHz，輸出頻率鎖定在5 GHz，鎖定時輸出時脈抖動量為10.3 ps(pk-pk)。鎖定時間為1.6 us，功率消耗為10.1 mW，晶片面積為924.58 924.58 um2，核心電路部分面積則為236.23313.54 um2。

摘要(英)

In this thesis, a fast locking PLL is proposed. Its oscillator is composed of 4-stage differential delay cells and can output 8 phase, 5 GHz clock signals without using inductors.The oscillator adopts multi-band architecture to lower the gain of the voltage controlled oscillator, KVCO, and the band selector picks out the adequate band to lock in. The adaptive phase frequency detector speed up the intra-band tracking so that the control voltage(VC)could vary agilely and the phase difference could be eliminated rapidly.
This study was implemented by TSMC 90 nm(TN90GUTM) 1P9M process with 1 V supply voltage. A 50 MHz clock is used to be input reference clock of PLL, and the output frequency is 5 GHz. The period jitter of output frequency is 10.3 ps(pk-pk). The locking time of the proposed PLL is 1.6 us at 5 GHz and the power consumption of the PLL is 10.1 mW.
The chip area is 924.58 924.58 um2 and the core area is 236.23 x 313.54 um2.

關鍵字(中)

★ 快速鎖定鎖相迴路
★ 電流匹配
★ 雙路徑技巧
★ 頻帶上加速機制
★ 頻帶選擇器
★ 可適性相位頻率偵測器

關鍵字(英)

★ Fast locking PLL
★ Current match
★ Dual path
★ Intra-band speedup
★ Band selector
★ Adaptive PFD

論文目次

目錄
摘要 ....................................................................................................................... i
Abstract ................................................................................................................. ii
誌謝 ..................................................................................................................... iii
目錄 ..................................................................................................................... iv
圖目錄 ................................................................................................................ vii
表目錄 ................................................................................................................. xi
第1 章緒論 ......................................................................................................... 1
1.1 研究動機 ................................................................................................. 1
1.2 論文架構 ................................................................................................. 2
第2 章快速鎖定鎖相迴路背景簡介 ..................................................................... 3
2.1 鎖相迴路簡介 .......................................................................................... 3
2.1.1 鎖定(Lock) .................................................................................... 4
2.1.2 規格考量 ....................................................................................... 4
2.2 快速鎖定鎖相迴路的不同做法 ................................................................. 5
2.2.1 使用非線性/分段線性相位頻率偵測器之快速鎖定鎖相迴路[1][2] .. 5
2.2.2 使用邊緣遺失補償器之寬鎖定範圍快速鎖定鎖相迴路[3] ............... 6
2.2.3 使用動態相位補償技術之快速鎖定鎖相迴路[4] ............................. 7
2.2.4 一個具有迅捷的電壓控制震盪器校正技術的鎖相迴路[5] ............... 9
2.2.5 具有快速精準的自我頻率校正機制之時脈產生器[6] .................... 10
2.2.6 輸出頻率為2.5GHz 具快速鎖定之自我校正鎖相迴路[9] .............. 11
第3 章快速鎖定鎖相迴路設計 ........................................................................... 13
3.1 設計概念 ............................................................................................... 13
3.1.1 選擇頻帶部分 .............................................................................. 13
3.1.2 追鎖過程 ..................................................................................... 15
3.2 預計規格 ............................................................................................... 16
第4 章快速鎖定鎖相迴路電路介紹 ................................................................... 19
4.1 電路架構 ............................................................................................... 19
4.2 穩定度分析 ........................................................................................... 21
4.3 行為模型(Behavior model) ...................................................................... 24
4.4 快速鎖定鎖相迴路子電路介紹 ............................................................... 25
4.4.1 頻帶選擇器 ................................................................................. 25
(a) 數位頻率偵測器 .............................................................................. 26
(b) 取樣器 ............................................................................................ 27
(c) 上下數產生器 .................................................................................. 29
(d) 溫度計碼計數器 .............................................................................. 29
(e) 閂鎖 ................................................................................................ 30
(f) 數位類比轉換器 .............................................................................. 30
4.4.2 可適性相位頻率偵測器 ............................................................... 33
4.4.3 基本鎖相迴路 .............................................................................. 35
(a) 相位頻率偵測器 .............................................................................. 36
(b) 單端轉雙端電路 .............................................................................. 38
(c) 電荷幫浦 ......................................................................................... 39
(d) 迴路濾波器 ..................................................................................... 40
(e) 電壓控制震盪器 .............................................................................. 41
(f) 電流模式緩衝器 .............................................................................. 44
(g) 雙端轉單端電路 .............................................................................. 45
(h) 除頻器 ............................................................................................ 47
第5 章晶片模擬結果與實現 .............................................................................. 49
5.1 快速鎖定鎖相迴路模擬結果 .................................................................. 49
5.1.1 頻帶選擇器模擬結果 ................................................................... 49
5.1.2 頻帶上加速機制模擬結果 ............................................................ 51
5.1.3 全電路模擬結果 .......................................................................... 52
5.2 逐一切換頻帶做法模擬 ......................................................................... 55
5.3 額外開啟電流做法模擬 ......................................................................... 57
5.4 窄頻寬條件模擬 .................................................................................... 58
5.5 晶片佈局 ............................................................................................... 60
5.6 電路規格 ............................................................................................... 63
5.7 量測考量 ............................................................................................... 64
第6 章結論與未來研究方向 .............................................................................. 67
6.1 結論 ...................................................................................................... 67
6.2 未來研究方向 ........................................................................................ 67
參考文獻 ............................................................................................................. 69

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2013-11-29

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