應用於雙速率串列傳輸系統之 時脈與資料回復電路

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姓名

呂耕維(Keng-Wei Lu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於雙速率串列傳輸系統之時脈與資料回復電路
(Dual-rate Clock and Data Recovery Circuit for Serial Link Data Transmission)

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摘要(中)

隨半導體產業發展與電腦相關產業的興起，資料傳輸頻寬逐漸上升，傳統並列傳輸方式漸漸被串列傳輸取代，例如DisplayPort、SATA、USB、及PCI-E等皆使用串列傳輸介面。本論文參考SATA 2/3規格實現一個時脈與資料回復電路，其中以鎖相迴路(Phase Lock Loop, PLL)為主體，並利用多頻帶閘控制電壓控制振盪器(Multi-band Gated-Voltage-Control-Oscillator, GVCO)實現兩種操作速率並降低電壓控制振盪器增益。
此論文使用TSMC 90 nm製程實現一個3/6 Gbps之雙速率時脈與資料回復電路(Clock and Data Recovery, CDR)，電路由四個部分所組成，分別是資料速率判斷電路、頻率資訊鎖相迴路、多頻帶閘控制電壓控制振盪器及時脈回復迴路。資料速率判斷用以偵測輸入資料的速率而調整電路頻寬與操作頻率；頻率資訊鎖相迴路可提供控制電壓與數位碼資訊供給多頻帶閘控制電壓控制振盪器對輸入資料進行解多工，將輸入資料速率降為原本的一半並且半速率(Half-rate)對齊輸入資料後再將對齊時脈送入時脈回復迴路；時脈回復迴路將還原出時脈以取樣輸入資料並還原資料。多頻帶閘控制電壓控制振盪器可實現兩種操作速率而避免使用多組不同振盪頻率之電壓控制振盪器，並且利用多頻帶之特性降低電壓控制振盪器增益，可降低電壓控制振盪器本身所造成的抖動。依據設計與模擬結果，抖動轉移函數頻寬為 2.1±1 MHz (SATA2)與4.2±2 MHz (SATA3)之間，在5 nH模擬打線電感之環境下，時脈峰對峰值抖動為28.3 ps(1.5 GHz) / 25.7 ps(3 GHz)，總面積為1252×1086 um2，電路核心面積580 416 um2，供應電源為1 V下，功率消耗為115 mW。

摘要(英)

In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, PCI-E. This study presents a clock and data recovery (CDR), and takes SATA 2/3 specification as reference material.
This study presents the CDR circuit fabricated in a 90-nm CMOS process and realizes a 3/6 Gbps dual-rate clock and data recovery. The CDR circuit consists of a frequency information phase-locked-loop, a data recovery loop, a multi-band gated-voltage-control-oscillator and a specification detector. The CDR employs a phase-lock-loop as the data recovery (DR) loop and the multi-band gated-voltage-control-oscillator which operates at dual frequency and reduces the voltage-control-oscillator gain. The specification detector detects the input data rate and modifies the operating frequency and bandwidth. The frequency information phase-locked-loop provides a analog voltage and digital codes to control the multi-band gated-voltage-control-oscillator which used to demux the input data into half-rate data streams. The data recovery loop recovers the recovered clock which samples input data and recovers data. The multi-band gated-voltage-control-oscillator operates at dual-rate without two oscillators and realizes the multi-band mechanism to reduce the jitter.
In terms of the CDR setting, conforming that the gain of error signal E(s) of -3 dB lies at the jitter frequency of 2.1±1 MHz (SATA2) and 4.2±2 MHz (SATA3). The 3/6 Gb/s input data is simulated with the 5 nH wire bonding and the peak-to-peak jitter of the recovered clock is 28.3 ps(1.5 GHz) / 25.7 ps(3 GHz). The whole chip area is 1252×1086 um2 and chip core area is 580 416 um2. The total power consumption is around 115 mW at supply voltage of 1 V.

關鍵字(中)

★ 鎖相迴路
★ 閘控制電壓控制振盪器
★ 時脈與資料回復電路

關鍵字(英)

★ Phase-locked loop
★ gated voltage control oscillator
★ Clock and data recovery

論文目次

目錄
摘要 iii
Abstract v
誌謝 vii
目錄 viii
圖目錄 xii
表目錄 xvi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章時脈資料回復電路之抖動考量 5
2.1 時脈抖動簡介 5
2.2 定量性抖動(Deterministic Jitter, DJ) 6
2.2.1 週期性抖動(Periodic Jitter, PJ) 6
2.2.2 資料相關抖動(Data Dependent Jitter, DDJ) 7
2.2.3 責任週期失真(Duty-Cycle Distortion, DCD) 8
2.3 隨機性抖動(Random Jitter, RJ) 9
2.4 眼圖分析 10
2.5 誤碼率(Bit Error Rate) 11
2.6 時脈資料回復電路抖動函數 13
2.6.1 抖動轉移函數(Jitter Transfer Function, JTF) 13
2.6.2 抖動容忍(Jitter Tolerance) 14
第3章時脈資料回復電路簡介 17
3.1.1 串列傳輸與並列傳輸 18
3.1.2 資料型態 18
3.2 取樣速率 19
3.3 時脈資料回復電路設計與比較 20
3.3.1 鎖相迴路式時脈資料回復電路 20
3.3.2 混合鎖相迴路/延遲鎖相迴路式時脈資料回復電路 22
3.3.3 超取樣式時脈資料回復電路 23
3.3.4 相位選擇式時脈資料回復電路 24
3.3.5 閘控制數位控制振盪器式時脈與資料回復電路 25
第4章應用於雙速率串列傳輸系統之時脈與資料回復電路 27
4.1 電路架構 27
4.2 操作說明 29
4.3 規格與系統分析 32
4.3.1 頻率資訊鎖相迴路系統分析 32
4.3.2 時脈回復迴路系統分析 36
4.4 電路設計 40
4.4.1 多頻段閘控制電壓控制振盪器(GVCO) 40
4.4.2 時脈回復迴路(Clock Recovered Circuit) 44
4.4.2.1 相位頻率偵測器(PFD) 45
4.4.2.2 電流幫浦(CP)與迴路濾波器(LPF) 48
4.4.2.3 除頻器 (Divider) 51
4.4.3 頻率資訊鎖相迴路(Frequency Information Phase Lock Loop) 52
4.4.3.1 自我校正機制(Self-Calibration Circuit) 53
4.4.4 鎖定偵測器 (Locked Detector) 57
4.4.5 資料速率判斷電路(Data Detecor) 58
4.4.5.1 數位頻率偵測器(Digital Frequency Detector) 59
4.4.5.2 規格判斷電路與暫存器(Spec. Detector & Register) 60
4.5 行為模型模擬-規格頻寬驗證 62
4.6 迴路模擬結果 64
4.6.1 頻率資訊鎖相迴路控制電壓模擬結果 64
4.6.2 頻率資訊鎖相迴路與時脈回復迴路控制電壓模擬結果 65
4.6.3 資料回復迴路模擬結果 67
4.6.4 頻寬測試模擬結果 69
4.7 規格比較表 74
第5章晶片佈局與量測考量 77
5.1 電路佈局 77
5.1.1 晶片封裝 78
5.1.2 佈局規劃與電源規劃 80
5.2 量測考量 81
5.2.1 量測環境 81
5.2.2 印刷電路板 82
5.2.3 輸入資料緩衝器 83
5.2.4 輸出時脈與資料緩衝器 84
5.3 晶片與印刷電路板照相 85
5.4 量測結果 86
5.4.1 輸入緩衝器量測 86
5.4.2 頻率資訊鎖相迴路量測 88
5.4.3 時脈回復迴路量測 89
第6章結論與未來研究方向 95
6.1 結論 95
6.2 未來改進方向 95
參考文獻 97

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2013-11-29

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