| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳進曜 | zh_TW |
| DC.creator | Chin-Yaw Chen | en_US |
| dc.date.accessioned | 2013-8-14T07:39:07Z | |
| dc.date.available | 2013-8-14T07:39:07Z | |
| dc.date.issued | 2013 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=100521011 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 由於類比電路元件的敏感性，製程技術快速地發展與元件尺寸大幅地縮小，使得考慮佈局之後的電氣效應以及面積變得非常重要。為了減少電氣效應對電路的影響，類比電路設計大多以人工方式產生佈局，雖然使用類比設計自動化搭配工程師的佈局經驗可以取代部分人工，但是眾多的佈局限制仍然是類比設計自動化發展的最大難題。
目前存在許多類比元件擺置的相關文獻，然而同時考慮到繞線的研究卻非常稀少。為了降低製程以及寄生效應對電路佈局產生的影響，一般常利用拓樸限制處理元件之間的不匹配，但繞線仍會對類比元件產生非預期的電氣效應。為了減少繞線對類比元件的影響，最佳的繞線路徑必須避開類比元件，且應避免過長的線長致使額外的電阻和延遲，因此，在擺置的過程中預留足夠的繞線空間並且限制導線的最大線長（maximal wire-length），以確保電路能達到預定的效能規格。
本論文提出一個在擺置階段同時考量繞線空間及限制每一條導線最長線長的類比自動化設計流程，可以完成元件擺置以及繞線結果。擺置過程中首先針對繞線路徑預留通道，接著提出二階段形狀曲線修剪技巧評估線段的最大線長以及面積的因素，產生符合效能規格並且保有較小面積的結果。最後搭配應用延遲決策技術（DDM）產生複數擺置結果，並且符合對稱、鄰近的擺置限制，提供工程師良好且彈性的選擇。 | zh_TW |
| dc.description.abstract | Due to the sensitivity of analog components, and the size shrink of devices, post-layout electrical effects increasingly impact the circuit performance. In order to reduce the impact of electrical effects on circuits, the layout of analog circuits are mostly generated by manual. Although layouts of partial designs can be done by EDA tools with experience of engineers, to overcome the complex layout constraints and close to the regarded of engineers are the urgent issues.
Although there are many literatures on analog placement, the number of researches on analog placement considering routing is few. In the placement process, though we can use the topology constraints to reduce the mismatch, the unexpected electrical effects will be produced by the routing paths. In order to reduce the electrical effects produced by the routing paths, routing paths must avoid passing through the analog devices, and the maximal wire-length of routing must be shortened. Implying that to preserve enough routing spaces and limit wire-length in the placement stage are needed.
This work presents an analog placement and routing flow to handle the symmetry constraints, to preserve enough routing spaces, and to limit maximal wire-length between devices. Preserving the routing channels first, then using a two-stage curve pruning technology to trade-off between area and maximal wire-length. The flow is based on the deferred decision making (DDM) technique. Using DDM technique cannot only generate non-stochastic solutions, but also provide multiple and flexible solutions for engineers. | en_US |
| DC.subject | 類比電路擺置 | zh_TW |
| DC.subject | 面積與最大線長最佳化 | zh_TW |
| DC.subject | 效能導向 | zh_TW |
| DC.subject | 佈局產生器 | zh_TW |
| DC.subject | Analog Circuit Placement | en_US |
| DC.subject | Area and Maximal Wire-length Optimization | en_US |
| DC.subject | Performance Driven | en_US |
| DC.subject | Layout Generator | en_US |
| DC.title | 面積與最大線長最佳化之類比積體電路 佈局產生器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Area and Maximal Wire-length Optimization of Analog ICs Layout Generator | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |