| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 彭韶驊 | zh_TW |
| DC.creator | Shao-hwa Peng | en_US |
| dc.date.accessioned | 2013-8-5T07:39:07Z | |
| dc.date.available | 2013-8-5T07:39:07Z | |
| dc.date.issued | 2013 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=100521066 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文之主軸是將chirp 信號及分數傅立葉轉換實現於FPGA，並將此
技術應用於大腦人機介面上，即Chirp 視覺誘發電位為基礎之大腦人機介面。
若想將chirp 信號及分數傅立葉轉換完美之實現於FPGA，需要耗費相當大
之記憶體，此將使成本提高。因此本篇提出了chirp 信號之分段差分最佳化
近似，以及分數傅立葉轉換之泰勒展開式近似，來分別將其實現於FPGA。
傳統以穩態視覺誘發電位為基礎之大腦人機介面，其刺激源皆為定頻訊號，
可控制刺激源數量之參數除了有限之頻帶，只有相位一種。且自然環境較
容易出現定頻雜訊，因此系統之訊雜比將會較容易受到影響。而Chirp
視覺誘發電位為基礎之大腦人機介面將可解決以上問題，控制刺激源數量
之參數變為刺激時間、頻率變化率與起始頻率三樣，且因為自然界幾乎不
會出現固定頻率變化率之雜訊，因此對於系統之SNR 將會有所改善。 | zh_TW |
| dc.description.abstract | This study implements Chirp signal and Fractional Fourier Transform in
FPGA, and the technique is applied to the BCI system, and it’s called
Chirp-VEP Based BCI System. If we want to implement Chirp signal and
Fractional Fourier Transform perfectly in FPGA, it will take a sizeable memory
and increase the cost. Therefore, this paper proposes Piecewise Differential
Optimized Approximation for Chirp signal, and the Taylor Series Approximation
for Fractional Fourier Transform to implement in FPGA. The signal source of
stimulation are all fixed-frequency on the traditional SSVEP Based BCI system,
in addition to limited bandwidth, only phase which are controllable parameters
of the number of signal source, and the general environment often exists
fixed-frequency noise, so the system SNR will be more susceptible. The
Chirp-VEP Based BCI System will resolve the above problem. The numbers of
controllable parameter of signal source are stimulation time, chirp rate, and
initial frequency; it’s more than traditional SSVEP Based BCI system. There is
almost no fixed rate of change of frequency in general environment, so the SNR
for the system will be improved. | en_US |
| DC.subject | Chirp 信號 | zh_TW |
| DC.subject | 分數傅立葉轉換 | zh_TW |
| DC.subject | 大腦人機介面 | zh_TW |
| DC.subject | 穩態視覺誘發電位 | zh_TW |
| DC.subject | Chirp 視覺誘發電位 | zh_TW |
| DC.subject | Chirp signal | en_US |
| DC.subject | Fractional Fourier Transform | en_US |
| DC.subject | BCI | en_US |
| DC.subject | SSVEP | en_US |
| DC.subject | Chirp-VEP | en_US |
| DC.title | Chirp視覺誘發電位為基礎之大腦人機介面 - FPGA實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Chirp-VEP Based BCI system – FPGA Implementation | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |