| dc.description.abstract | A CMOS power amplifier (PA) with wideband, high output power and high efficiency is the most challenging circuit due to low-Q passive component, lossy substrate, low breakdown voltage and low maximum available gain (MAG) of the transistors, especially in millimeter-wave frequency. Therefore, broadband and low-loss impedance transformers are attractive especially in CMOS PAs. The contents of this thesis are divided into five parts. Chapter 1 gives the motivation of system applications. Chapter 2 introduces the basic theory and some design parameters of power amplifier. Chapter 3 presents several fully-integrated wideband PAs were fabricated in tsmcTM 0.18-μm and 90-nm CMOS technologies. The focus of this chapter is the research of transmission-line transformers (TLTs). TLTs can be exploited to perform broadband and low-loss impedance transformation. Therefore, three wideband PAs were designed by utilizing broadband and low-loss Guanella-type TLT as the matching networks with different frequency bands.
A full X-band PA with an integrated Guanella-type transformer and a pre-distortion linearizer in 0.18-µm CMOS was implemented in the first design. The broadband performance was achieved by using transformers including a differential Guanella-type TLT (DTLT) and two magnetically coupled transformers. The linearity of PA is enhanced by feedback topology and the use of pre-distortion linearizer. Over full X-band from 8 GHz to 12 GHz, the saturated output power (Psat) and the maximum power added efficiency (PAEmax) are higher than 21.3 dBm and 16.19%, respectively. The performances of output 1-dB gain compression point (OP1dB) and PAEP1dB are significantly improved by an output power of 2.2 dBm and a PAE of 12.1%, which contributes to power back-off operation for the application of linear modulation. The chip area, including pads, is 1.05 mm2.
In the second design, an 18 to 33 GHz fully-integrated Darlington PA with DTLTs demonstrated the wideband and high power performance compared with other Ka-band CMOS PAs. The Darlington cell with cascode topology was adopted as the power cell to elevate the MAG of the transistors in standard 0.18-μm CMOS technology for being capable of operating at Ka band. Moreover, utilizing broadband and low-loss DTLTs as the matching networks, the proposed PA exhibits a flat gain of 15.2±1 dB from 17.8 to 34.6 GHz. The 3-dB power bandwidth is from 18 to 33 GHz with the saturated output power of 19.5 dBm. The OP1dB of 16 dBm and PAE of 10.2% are achieved at 26 GHz under a power consumption of 711 mW. The chip size is 0.86 mm2 including test pads.
In the third disign, a wideband Darlington power amplifier using DTLTs and current-reused technique was fabricated in 90-nm CMOS technology for V-Band applications. Compare to the original Darlington topology, the proposed current-reused Darlington topology achieve the same gain-extension ability while consumes less current than that of conventional one. This wideband PA exhibits a peak gain of 16.4 dB, and 3-dB bandwidths from 33.3 to 59.3 GHz. The measured result shows the saturated power of 9.9 ± 0.6 dBm from 35 to 60 GHz. The OP1dB of 5.3 dBm and PAE of 4.8% are achieved at 50 GHz.
Chpater 4 develops a compact-size transmitter front-end for 24-GHz Frequency- Modulated Continuous-Wave (FMCW) applications, which is composed of voltage-controlled oscillator (VCO), frequency doubler and medium power amplifier. The measured oscillation central frequency is 23.7 GHz with the tunable frequency range from 22.8 to 24.5 GHz. The phase noise is -99.1 dBc/Hz at 1-MHz offset, and the maximum output power is 15.3 dBm. The total power consumption is 225 mW.
Finally, the conclusion and future work are given in Chapter 5. | en_US |