| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系 | zh_TW |
| DC.creator | 陳德龍 | zh_TW |
| DC.creator | Te-lung Chen | en_US |
| dc.date.accessioned | 2014-8-22T07:39:07Z | |
| dc.date.available | 2014-8-22T07:39:07Z | |
| dc.date.issued | 2014 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=100523021 | |
| dc.contributor.department | 通訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | DVB-T(Digital Video Broadcasting - Terrestril)為歐洲廣播聯盟(European Broadcast Union，EBU)制定的數位電視廣播網路系統規格，也是台灣目前採用的數位電視廣播系統。
在本文中，我們採用目前台灣數位電視廣播的規格，設計並且實現DVB-T的基頻傳送端即時硬體實現以及使用FPGA進行驗證。發射端的硬體架構包含了以下的主要模組：里德-所羅門碼編碼器，外交錯器、迴旋碼編碼器、打孔器、內交錯器(bit、symbol)、快速反傅利葉處理器、循環前綴產生器以及生取樣器，設計問題方面有多速率運作模組間的整合與同步、快速反傅利葉處理器在定點數上的解析度以及低通濾波器在數位升取器的使用。
在設計階段上，我們首先使用MATLAB進行建模與分析，已獲得適當的系統性能/精準度以來估計硬體複雜度來獲得適當的設計。在實驗階段，Verilog硬體描述語言用於使用邏輯行為來描述其硬體架構與及時系統，時序模擬使用ModelSim，硬體驗證使用FPGA。
及時驗證於基頻發射機是經由此發射機發射一DVB-T訊號載上一較低的中頻載波後，經由電力線通道來實現與展示。及時發射機包含了FPGA以及數位類比轉換器及電力線通訊類比前級電路
。發射的DVB-T訊號經由另一個電力線通訊接收模塊收回後，以離線後以接收機的演算法來分析接收到的訊號。 | zh_TW |
| dc.description.abstract | Digital Video Broadcasting–Terrestrial (DVB-T) is the digital television broadcasting standard specified by the European Broadcasting Union, which is also adopted in Taiwan.
In this thesis, we design and realize a real-time hardware baseband transmitter for DVB-T using FPGA. The architecture of the transmitter is comprised of the following main modules: Reed-Solomon code encoder, outer interleaver, convolutional code encoder with puncher, innner interleaver (bit, symbol), IFFT processor, Cyclic-Prefix generator and digital-upconverter. The design issues include interfacing/synchronization between multi-rate modules, fixed-point resolution of the IFFT processor and the lowpass filter in the digital-upconverter. In the design phase, we first use MATLAB for modeling and analysis to obtain an appropriate design which tradeoffs the system performance/accuracy with estimated hardware complexity. In the implementation phase, Verilog hardware description language is used for coding the hardware system followed by logic behavior and real-time verifications with ModelSim and FPGA platform, respectively.
The real-time verification of the baseband transmitter is achieved by a realization and demonstration of a real-time transmitter which transmits the DVB-T signal with a lower IF carrier through the power-line channel. The real-time transmitter comprises of the FPGA platform which is loaded with the transmitter design, the Digital-to-Ananlog module and the power-line communication (PLC) analog frontend. The transmitted DVB-T signal is captured by another PLC receiver platform and then is analyzed by off-line receiver algorithm which verifies the real-time transmitted signal. | en_US |
| DC.subject | 數位電視廣播 | zh_TW |
| DC.subject | 電力線通訊 | zh_TW |
| DC.subject | 正交分頻多工 | zh_TW |
| DC.subject | 現場可程式化邏輯陣列 | zh_TW |
| DC.subject | Digital Video Broadcasting | en_US |
| DC.subject | OFDM | en_US |
| DC.subject | Power Line Communication | en_US |
| DC.subject | FPGA | en_US |
| DC.title | DVB-T基頻發射機之FPGA硬體設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and FPGA Implementation of Baseband Transmitter for DVB-T System | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |