| dc.description.abstract | In recent years , according to Moore’s law, the electronic related products have been promoted on function and execution speed concepts and trend to light and thin design. A case study of smart phone, it is not only light and thin design, but also high pixel. So semi-conductor under the package size getting smaller and execution speed become faster, package process become lead design closer to induce defect occurrence. Therefore, consider process yield and products cost, defect improvement is needed.
In this thesis second chapter and chapter third, focus on Wafer Level Chip Scale Package Redistribution layers exposure process photo resistance residue problems, discuss the theoretical mechanisms occurrence. Mainly by the RDL exposure intensity, exposure time, exposure method, passivation layer roughness and use Taguchi methods to find out the optimized conditions to solve PR residue problems.
The fourth chapter, discuss RDL exposure process photoresist residue problems occurs from unsuitable exposure intensity and long exposure time, induce high reflection light between chip and chip. Hence, impact RDL exposure process PR residue ratio. To reduce exposure distance between mask and wafer and rise passivation layer roughness, both conditions could avoid diffusion to induce reflection light effectively. Taguchi method result: exposure intensity 4mw/cm2, exposure time 65sec, soft contact is the optimized condition. | en_US |