| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳柏勳 | zh_TW |
| DC.creator | Po-Hsun Chen | en_US |
| dc.date.accessioned | 2014-7-2T07:39:07Z | |
| dc.date.available | 2014-7-2T07:39:07Z | |
| dc.date.issued | 2014 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=101521036 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文利用tsmc提供的0.18-μm CMOS 與90-nm CMOS製程設計功率放大器，在設計上分成兩部份，第一部份為tsmc 0.18-μm CMOS製程設計功率放大器以操作於K頻段功率放大器為主要目標。運用傳輸線型變壓器和磁耦合變壓器達到寬頻與低損耗的阻抗匹配，以及使用交錯耦合單向化電容抑制共源結構中由於閘-汲寄生電容（Cgd）所產生的密勒效應（Miller Effects），提高放大器電路的隔離度、穩定性和提升傳輸增益（S21），達成高隔離度和高增益之功率放大器；第二部份為全積體整合矽製程tsmc 90-nm CMOS設計於V頻段之寬頻功率放大器，使用T型傳輸線寬頻匹配技術，以及串接三級電晶體串疊架構達到寬頻功率放大器。
各電路特性量測如下：應用於K頻段之單向化差動功率放大器，傳輸增益（S21）為26.2 dB，反向傳輸增益（S12）低於-60 dB，飽和輸出功率為20.6 dBm，1-dB增益壓縮點輸出功率為17 .2 dBm，功率增進效率為16%， 3-dB頻寬為4 GHz（19.2 GHz至23.2 GHz）；應用傳輸線型變壓器於K頻段高增益單向化功率放大器，傳輸增益（S21）為26.2 dB，反向傳輸增益（S12）低於-58 dB，飽和輸出功率為20.3 dBm，1-dB增益壓縮點輸出功率為17 .2 dBm，功率增進效率為24.1%， 3-dB頻寬為4.5 GHz（18.8 GHz至23.3 GHz）；V頻段寬頻功率放大器，傳輸增益（S21）為17.8 dB，飽和輸出功率為11.4 dBm，1-dB增益壓縮點輸出功率為7.2 dBm，功率增進效率為4.4%， 3-dB頻寬（受限於量測儀器只能量測到67 GHz）為19.8 GHz（47.2 GHz至67 GHz）。 | zh_TW |
| dc.description.abstract | Both K-band and V-band fully integrated silicon-based power amplifiers are designed in this thesis, which are fabricated in tsmc 0.18-μm and 90-nm CMOS processes, respectively.
In the first part, the power amplifier adopted a neutralization topology to mitigate the intrinsic gate-drain feedback of each transistor to increase power gain and reverse isolation. The amplifier consists of three differential stages that are used transformers for impedance matching and inter-stage coupling. The 3-dB bandwidths are from 19.3 to 23.3 GHz with reverse isolation better than 60 dB. The amplifier achieves a power gain of 26.2 dB, a saturated output power of 20.6 dBm, an output 1-dB gain compression point of 17.2 dBm and a power added efficiency of 16.2%. The chip size is 1.11 mm2 with pad.
In the second part, we use transmission-line transformers for the input and output matching networks. The 3-dB bandwidths are from 18.8 to 23.5 GHz with reverse isolation better than 58 dB. The amplifier achieves a power gain of 26.2 dB, a saturated output power of 20.3 dBm, an output 1-dB gain compression point of 17.4 dBm and a power added efficiency of 24.1%. The chip size is 1.11 mm2 with pad.
In the third part, a wideband V-band power amplifier is implemented by adopting wideband matching network technique. The V-band power amplifier with wideband in tsmcTM 90-nm CMOS Technology achieves a power gain of 17.8 dB, a saturation output power of 11.4 dBm, an output power at 1-dB gain compression point of 7.2 dBm, and a power added efficiency of 4.4%. The 3-dB bandwidths are from 47.2 to 67 GHz. The chip size is 0.57 mm2 with pad. | en_US |
| DC.subject | 功率放大器 | zh_TW |
| DC.subject | 傳輸線型變壓器 | zh_TW |
| DC.subject | 單向化電路 | zh_TW |
| DC.subject | Power Amplifier | en_US |
| DC.subject | TLT | en_US |
| DC.subject | Unilateralization | en_US |
| DC.title | 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Implementation on Fully Integrated Unilateralized CMOS Power Amplifiers for K-band Applications and Wideband Power Amplifier for V-band Applications | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |