| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 葉仲維 | zh_TW |
| DC.creator | Chung-wei Yeh | en_US |
| dc.date.accessioned | 2013-8-21T07:39:07Z | |
| dc.date.available | 2013-8-21T07:39:07Z | |
| dc.date.issued | 2013 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=101521087 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在印刷電路板設計中，印刷電路板的規模變得愈大且愈複雜。交錯腳位陣列，一種新的結構被提出用以解決高腳位密度的問題。雖然逃脫繞線(escape routing)在高速印刷電路板佈線已經成為一個極為重要的問題，然而先前大部分的研究都集中在單一種類訊號的逃脫繞線，例如：差動對訊號或單訊號。先前的研究[12]提出了一種在交錯腳位陣列上的兩段式混合訊號逃脫繞線演算法;然而，由於他們建模(modeling)及繞線方法上的缺陷，所以未能完全成功處理二種訊號的逃脫繞線（差動對訊號和單訊號）。在這篇論文中，我們提出了一個在交錯腳位陣列上符合差動對訊號的線長匹配條件並且能同步處理混合訊號的逃脫繞線演算法。此演算法採用整數線性規劃，以能同時完成所有單訊號和差動對訊號的逃脫繞線。與二段式演算法比較，提出的演算法可以得到更好的逃脫繞線結果。實驗結果顯示，這種方法對於混合訊號問題的處理是相當有效的，可以降低導線長度以及達到100％線長匹配和可繞度 | zh_TW |
| dc.description.abstract | In PCB designs, the scale of PCB becomes larger and more complex. A new structure, the staggered pin array, is provided to address the high pin density problem. Although escape routing has become a critical issue in high-speed PCB routing, most of previous works focus on only differential-pair escape routing or single-signal escape routing. Previous work [12] has proposed a two-stage approach to the routing of mixed-pattern signals on staggered pin arrays; however, they failed to route two kinds of nets (differential pair and single signal) totally due to the defects of the modeling and the routing method. In this thesis, a simultaneous escape routing algorithm for the differential-pair nets with length matching and single-signal nets on staggered pin arrays is proposed. This algorithm adopts integer linear programming to simultaneously route all single-signal and differential-pair nets. Compared with a two-stage method, we can find better solutions for escape routing. Experimental results show the efficacy of this approach, which can significantly handle the mixed-pattern signals problem and reduce wire length under 100% length-matching and routability. | en_US |
| DC.subject | 逃脫繞線 | zh_TW |
| DC.subject | escape routing | en_US |
| DC.title | Simultaneous escape routing for mixed-pattern signals on staggered pin arrays | en_US |
| dc.language.iso | en_US | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |