| dc.description.abstract | In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, and PCI-E. This study presents a clock and data recovery (CDR), and takes the DisplayPort specification as reference material.
In this thesis, a CDR with adaptive gain control is proposed. The adaptive gain control circuit measures the jitter of recovered clock to detect the input data implied high-frequency or low-frequency jitter at the moment. By adjusting the bandwidth of data recovery loop, the clock and data recovery circuits can improve jitter tolerance at high-frequency and low-frequency. At 5.4 Gbps data rate, CDR jitter tolerance improvement is 60.9 percent at high-frequency, and 81.6 percent at low-frequency. This proposed was implemented by TSMC 90 nm (TN90GUTM) 1P9M process with 1 V supply voltage. When input data rate is at 5.4 Gbps, the recovered clock rate is 2.7 GHz. The period jitter of the output recovered clock is 23.11 ps (p-p). The power consumption of the CDR is 24.8 mW. The chip area is 1260 1178 um2 and the core area is 323 329 um2.
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