| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 殷鼎欽 | zh_TW |
| DC.creator | Din-chin Yin | en_US |
| dc.date.accessioned | 2015-7-13T07:39:07Z | |
| dc.date.available | 2015-7-13T07:39:07Z | |
| dc.date.issued | 2015 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=101521124 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 佈局的自動化設計在類比電路上可以大幅的降低設計時的高錯誤率、高複雜度的佈局操作所花費的時間與繁瑣的任務和昂貴的設計成本。由於敏感的寄生電容效應、元件的不匹配、製程變動與梯度效應都將導致佈局結果可能是一個不好的佈局，也造成了產品的不準確性與良率的降低。多數類比電路像是類比數位/數位類比轉換器或濾波器等等，其性能都依賴於準確的電容比值。對於要求準確的電容比值大都會使用多顆單位電容並聯取代單一顆大電容並考慮繞線引起的寄生效應，以減少一些不匹配的影響。
現存有許多種指標去衡量一個電容陣列，有鑑於此本論文比較了多個指標，並且使其往一特定方向統合，縮減成績分非線性(INL)和有效位數(ENOB)兩個指標，使得使用者能更快速的利用這兩個指標去判斷不同擺放之間的優劣。
| zh_TW |
| dc.description.abstract | Automated layout design on analog circuits can significantly reduce the high error rate of the design, the time complexity of the layout of the high cost of operation and tedious task and expensive design costs. Due to the mismatch sensitive parasitic capacitance effects, components, process variation and gradient effect will lead to the layout result can be a bad layout, also caused inaccuracies and lower product yield. Most of analog circuits such as analog-digital / digital-to-analog converters or filters, etc., and its performance is dependent on accurate capacitance ratio. For most of the requirements of the exact capacitance ratio of the capacitor in parallel using multiple satellites units substituted single and considering a large parasitic capacitance caused by winding, in order to reduce some of the effects of the mismatch.
Now there are too many metric to judging a capacitor array, so we need to unified them into a more accurate indicator. Thus the user can more quickly determine the advantages and disadvantages between the different displays. To let users to assess whether the results meet their desired capacitance.
| en_US |
| DC.subject | 動態性能指標 | zh_TW |
| DC.title | 二幂次電容區塊陣列排列的動態效能指標 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |